Current-flow and current-density-aware multi-objective optimization of analog IC placement

Martins, Ricardo; Póvoa, Ricardo; Lourenço, Nuno; Horta, Nuno

doi:10.1016/j.vlsi.2016.05.008

Cited by 22 publications

(28 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Let σ 1 , σ 2 be a symmetry pair [31][32][33] that refers to two matched cells placed symmetrically in relation to S v (P i ), with bottom-left coordinates σ 1 ,…”

Section: Methods 1 Quantum Wiring Optimization and Objective Function mentioning

confidence: 99%

“…The simultaneous physical-layer minimization and the maximization of the objective function are achieved by the Quantum Triple Annealing Minimization (QTAM) algorithm. The QTAM algorithm utilizes the framework of simulated annealing (SA) [31][32][33][35][36][37][38], which is a stochastic point-to-point search method.…”

Section: System Modelmentioning

confidence: 99%

“…In the QTAM algorithm, we take into consideration that the objectives, constraints, and other functions of the method, by some fundamental theory, are characterized by different magnitude ranges [31][32][33][35][36][37][38]. To avoid issues from these differences in the QTAM algorithm we define three annealing temperatures, T f (t) for objectives, T g (t) for constraints and T c (t) for the probability distribution closeness (distance of the output distributions of the reference quantum circuit and the reduced quantum circuit).…”

Section: Computational Modelmentioning

confidence: 99%

“…The optimization at several different objective functions results in different Pareto fronts [31][32][33]35] of placements of quantum gates in the physical layout. These Pareto fronts allow us to find feasible tradeoffs between the optimization objectives of the QTAM method.…”

Section: Constraint Violationsmentioning

confidence: 99%

See 3 more Smart Citations

Quantum circuit design for objective function maximization in gate-model quantum computers

Gyöngyösi

Imre

2019

Quantum Inf Process

View full text Add to dashboard Cite

Gate-model quantum computers provide an experimentally implementable architecture for near term quantum computations. To design a reduced quantum circuit that can simulate a high complexity reference quantum circuit, an optimization should be taken on the number of input quantum states, on the unitary operations of the quantum circuit, and on the number of output measurement rounds. Besides the optimization of the physical layout of the hardware layer, the quantum computer should also solve difficult computational problems very efficiently. To yield a desired output system, a particular objective function associated with the computational problem fed into the quantum computer should be maximized. The reduced gate structure should be able to produce the maximized value of the objective function. These parallel requirements must be satisfied simultaneously, which makes the optimization difficult. Here, we demonstrate a method for designing quantum circuits for gate-model quantum computers and define the Quantum Triple Annealing Minimization (QTAM) algorithm. The aim of QTAM is to determine an optimal reduced topology for the quantum circuits in the hardware layer at the maximization of the objective function of an arbitrary computational problem.

show abstract

“…Let σ 1 , σ 2 be a symmetry pair [31][32][33] that refers to two matched cells placed symmetrically in relation to S v (P i ), with bottom-left coordinates σ 1 ,…”

Section: Methods 1 Quantum Wiring Optimization and Objective Function mentioning

confidence: 99%

Section: System Modelmentioning

confidence: 99%

Section: Computational Modelmentioning

confidence: 99%

Section: Constraint Violationsmentioning

confidence: 99%

See 2 more Smart Citations

Quantum circuit design for objective function maximization in gate-model quantum computers

Gyöngyösi

Imre

2019

Quantum Inf Process

View full text Add to dashboard Cite

show abstract

“…In the interest of floorplanning, an initial step to govern the wire length, there is an urge for Electron migration-aware floor plans [7]. Hence, this paper analyzes the Skewed Binary tree (SKB) floorplanning representation, which is based on the Binary tree [8]. From the motivation of its analytical framework, this paper examines the performance of floor planner on Voltage drop and Electron Migration risk…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Srinath¹,

Priya²,

Kasliwal³

2018

IJET

View full text Add to dashboard Cite

In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.

show abstract

Related Work

Rosa¹,

Guerra²,

Horta³

et al. 2019

Using Artificial Neural Networks for Analog Integrated Circuit Design Automation

View full text Add to dashboard Cite

Current-flow and current-density-aware multi-objective optimization of analog IC placement

Cited by 22 publications

References 22 publications

Quantum circuit design for objective function maximization in gate-model quantum computers

Quantum circuit design for objective function maximization in gate-model quantum computers

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

Related Work

Contact Info

Product

Resources

About