Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding

Huyghebaert, Cedric; Olmen, J. Van; Civale, Yann; Phommahaxay, Alain; Jourdain, Anne; Sood, Sumant; Farrens, Shari; Soussan, Philippe

doi:10.1109/iitc.2010.5510444

Cited by 20 publications

(8 citation statements)

References 3 publications

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“…Variations on W2W thermo-compression bonding may involve the use of a polymer such as BCB at the interfaces of interest, resulting in a hybrid Cu-Cu thermo-compression bond [15][16][17]. Researchers have been able to show that such hybrid bonding can result in yields of 96% for structures with 10 µm pitch TSV's [16].…”

Section: W2w (Wafer To Wafer) Bondingmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Section: W2w (Wafer To Wafer) Bondingmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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“…TSVs fabrication includes several key steps such as DRIE, via filling, metallization, wafer thinning, alignment, and bonding [3], [7]. A typical via-first (via formation before CMOS process) can be summarized as follows.…”

Section: Tapered Tsvs: Inevitable Byproduct Of Manufacturing a Tmentioning

confidence: 99%

Modeling and Layout Optimization for Tapered TSVs

Srivastava

2015

IEEE Trans. VLSI Syst.

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Through-silicon-via (TSV) offers vertical connections for 3-D ICs. Due to its large dimensions and nonideal etching process, TSVs layout needs to be carefully optimized to balance peak current density and delay for digital circuit. This brief investigates the TSVs tapering effect (which is an inevitable byproduct of deep reactive Ion etchingbased manufacturing) and its impact on the TSVs electrical properties. We show that the current crowding effect is more severe in realistic tapered TSVs than ideal cylindrical TSVs. We propose a nonuniform current density model for tapered TSVs, which achieves considerable accuracy and speedup in estimating the current density distribution, when compared with the existing models developed for cylindrical TSVs. We apply our model to perform a detailed study on: 1) impact of TSVs tapering on peak current density and 2) wire sizing problem to minimize TSV-involved path delay under second-order delay model while keeping the peak current density within tolerable levels. A new dynamic programming-based heuristic is proposed to find the optimal wire configuration, which reduces both peak current density and delay, thereby improving the reliability and performance.

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“…In order to thin the wafer, the device wafer (Si interposer) is temporally bonded onto a carrier wafer [13,17]. Step2…”

Section: Substrate Thiningmentioning

confidence: 99%

TSV-based 3D integration fabrication technologies: An overview

Salah¹

2014

2014 9th International Design and Test Symposium (IDT)

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3D Integration is a promising and attractive solution for interconnect bottleneck problem, transistor scaling physical limitations, and impractical small-scale lithography. 3D integration extends Moore's law in the third dimension, offering heterogeneous integration, higher density, lower power consumption, and faster performance. However, in order to fabricate 3D ICs, new capabilities are needed: process technology, physical modeling, physical design tools, 3D architectures, design methods and tools. The goal of this paper is to cover the manufacturability of TSV-based 3D-ICs i.e. process technology, and fabrication capability.Index Terms-3D technologies, TSV, 3D Process, 3D Technology, 3D Integration, 3D fabrication. NOMENCLATURE FEOLFront-End-Of-Line. BEOLBack-End-Of-Line. TSV Through silicon via. 3D Three Dimensional DRIE Deep reaction ion etching. PECVD Plasma enhanced chemical vapor deposition. CMP Chemical mechanical polisher. KGD Known good die ESD Electrostatic discharge SEM Scan electron microscope SOI Silicon on insulator.

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Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding

Cited by 20 publications

References 3 publications

3D integration review

3D integration review

Modeling and Layout Optimization for Tapered TSVs

TSV-based 3D integration fabrication technologies: An overview

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