Analytical model of the 'terminal effect' during copper electrodeposition onto resistive wafers under Tafel kinetics is presented. Approximate analytical expressions for the plating current density and the potential distribution in the seed layer are derived for two domains: (a) close to the wafer edge, where the current and potential variations are large; and (b) Away from the wafer edge, where the current and potential variations are relatively small. A criterion for demarcating the two domains is formulated. Analytical model predictions agree reasonably well with numerical simulations of the non-uniform current distribution observed during copper electrodeposition onto highly resistive wafers.Nano-scale copper (Cu) interconnects in microprocessors and memory devices are fabricated by electrodeposition. 1 The interconnect metallization process involves several process steps: (i) sputter deposition of a Cu diffusion barrier (e.g., TaN), (ii) sputter deposition of a thin Cu seed layer, (iii) "bottom-up" electrodeposition of Cu to achieve void-free gap-fill, and (iv) chemical mechanical polishing to remove the excess Cu overburden. These process steps are implemented on 300mm wafers using advanced equipment and tools designed to provide excellent macro-scale uniformity. However, as interconnect dimensions shrink, 2 maintaining macro-scale uniformity becomes challenging. One scenario arising from continued interconnect scaling is the need for reducing the thickness of the Cu seed layer in order to prevent pinch-off and allow enough opening for the subsequent Cu electrodeposition step. Reducing the thickness of the Cu seed layer makes the substrate resistive and worsens the 'terminal effect' during electrodeposition. For Cu seed layers less than 10nm thick, the substrate resistivity can exceed 10μ -cm corresponding to a sheet resistance above 10 /sq. Additionally, the development of novel directly plate-able barriers 3 with sheet resistance exceeding several hundred /sq introduces even bigger challenges in achieving wafer-scale uniformity during electrodeposition. Another challenge for current distribution control may arise from the proposed transition in wafer diameter from 300mm to 450mm. Thus, characterizing the current distribution during electrodeposition onto resistive wafers is critical to electrochemical reactor design and scale-up.In published literature, the current distribution on resistive electrodes has been computed by employing numerical, semi-analytical or analytical methods. 4-7 Numerical simulations, while useful in computing the current distribution in complex geometries, are not generic and therefore, not useful in characterizing the precise form of the current or potential function. Analytical models, on the other hand, are not applicable to complex geometries, but are powerful in elucidating the exact nature of dependencies of the current or potential function on the system parameters. In context of wafer metallization, current distribution has also been treated numerically and analytically. Wi...