Crystallization at initial stage of low-temperature polycrystalline silicon growth using ZnS buffer layer with 〈111〉 preferred orientation

Abstract

We developed a low-temperature growth technique for polycrystalline silicon (poly-Si). When Si is deposited on glass substrates at 450 °C, it crystallizes as thickness increases, but 10-nm-thick layers of Si are mainly amorphous. Use of a ZnS buffer layer with 〈111〉 preferred orientation facilities crystallization of Si during the initial growth stages. The preferred orientation of poly-Si on glass substrates is 〈110〉, while that of poly-Si on the ZnS buffer layer is 〈111〉. This is probably due to local epitaxial growth on polycrystalline ZnS grains with 〈111〉 preferred orientation. Raman spectroscopy showed that the ZnS buffer layer significantly improved the crystallinity of 25-nm-thick Si layers.

Low-temperature (<450 °C), plasma-assisted deposition of poly-Si thin films on SiO2 and glass through interface engineering

“…2 Matsumoto et al utilized ͗111͘ oriented ZnS buffer layers, grown using diethyl zinc ͑DEZ͒ and H 2 S precursors, before initiating bulk film growth. 3 Using a similar approach, this study reports on lowtemperature poly-Si thin film deposition through interface engineering, or two-stage processing. The foundational basis for this interface engineering approach is derived from consideration that as deposition temperature decreases, crystallization becomes difficult during the initial stages of film growth due to poor surface mobility of adatoms and the lack of ordered sites found on the starting amorphous oxide surface.…”

Hydrogenated Microcrystalline Silicon Film Growth by Inductively Coupled Plasma–Chemical Vapor Deposition on ZrO2 Gate Dielectric for Thin Film Transistors

“…Crystal seed layer, which provides nucleation sites, was investigated to reduce the thickness of incubation layer. 3) However this crystal seed layer may not be adequate as gate dielectric of TFT. The requirement of gate dielectric in TFT are as following: 4,5) 1) The dielectrics must have a large energy of formation, so they do not react with mc-Si:H. 2) They should form high quality interfaces with mc-Si:H. 3) The conduction band should be larger offset of over 1 eV in order to suppress low leakage currents.…”

Growth of polycrystalline silicon at 470 °C by magnetron sputtering onto a sputtered μc-hydrogenated silicon seed layer

“…2 For direct px-Si film deposition, the limited nucleation rate at low temperatures always results in a thick amorphous silicon interface layer between the glass substrate and px-Si film. 4 In this letter, we report the growth of px-Si with meangrain diameter ϳ400 Å using dc reactive magnetron sputtering ͑RMS͒. Heath et al report a direct deposition process at temperatures of 540-575°C, in which Si nanocrystals are produced by excimer laser photolysis, and then px-Si is deposited by thermal chemical vapor deposition ͑CVD͒.…”

“…[1][2][3][4] The process temperature is limited by the softening temperature of the glass substrates ͑ϳ600°C for Corning 7059͒. [1][2][3][4] The process temperature is limited by the softening temperature of the glass substrates ͑ϳ600°C for Corning 7059͒.…”