Crystalline Oxides on Silicon – Alternative Dielectrics for Advanced Transistor Technologies

Abstract

Since the advent of the integrated circuit in 1959 and the introduction of MOS capacitors in the early ‘60’s, electronic technology has relied on silica (SiO2) as the gate dielectric in a field effect transistor. However, silica-based transistor technology is approaching fundamental limits. Feature-size-reduction and the ever-demanding technology roadmaps have imposed scaling constraints on gate oxide thickness to the point where excessive tunneling currents make transistor design untenable; an alternative gate dielectric is needed. Crystalline oxides on silicon (COS), simply by virtue of their high dielectric constants, could fundamentally change the scaling laws for silicon-based transistor technology. More importantly, COS could provide the opportunity for an entirely new device physics based on anisotropic response of crystalline oxides grown commensurately on a semiconductor. In this paper, we report that high dielectric constant alkaline earth and perovskite oxides can be grown in perfect registry with silicon. Commensurate heteroepitaxy between the semiconductor and the oxide is established via a sequenced transition that uniquely addresses the thermodynamics of a layer-by-layer energy minimization at the interface. The perfection of the physical structure couples directly to the electrical structure, and we thus obtain the unparalleled result of an equivalent oxide thickness of less than I nm in a MOS capacitor. With this demonstration it is apparent that COS presents a functional alternative to SiO2. With COS, a transistor gate can not only exhibit a much higher dielectric response, but add entirely new capabilities such as logic-state retention with the anisotropic response of ferroelectric polarization in a ferro-gated device. COS is the basis for fundamental change in semiconductor technology.

Epitaxial perovskite thin films grown on silicon by molecular beam epitaxy

“…MBE as-grown crystalline perovskite films on Si͑001͒ without an amorphous interfacial layer have been reported by using Z-contrast scanning transmission electron microscopy ͑TEM͒. 10,11 In this article, we report on epitaxial perovskite SrTiO 3 thin films on Si͑001͒ substrates. Structural, optical, and electrical properties are characterized using in situ reflection high energy electron diffraction ͑RHEED͒, x-ray diffraction ͑XRD͒, atomic force microscopy ͑AFM͒, high-resolution cross-sectional transmission electron microscopy ͑HRX-TEM͒, spectroscopic ellipsometry ͑SE͒, Auger electron spectroscopy ͑AES͒, Rutherford backscattering spectroscopy ͑RBS͒, current-voltage (I -V) and capacitance-voltage (C -V) measurements.…”

“…So far, there have been a few reports of successful STO growth on Si substrate using pulsed laser deposition, 14-16 e-beam deposition, 17,18 and molecular beam epitaxy ͑MBE͒. [10][11][12]19 Among the growth techniques, MBE offers the best control over the quality of the STO film and the oxide Si interface. MBE as-grown crystalline perovskite films on Si͑001͒ without an amorphous interfacial layer have been reported by using Z-contrast scanning transmission electron microscopy ͑TEM͒.…”

Field effect transistors with SrTiO3 gate dielectric on Si

“…This material has extremely high bulk dielectric constant and can be grown epitaxially on Si. [10][11][12][13][14] In this letter we present results for a SrTiO 3 /Si MOSFET with gate capacitance exceeding the capacitance of a 10 Å SiO 2 /Si MOSFET. The MOSFETs were fabricated by first forming n and p wells in a Si substrate.…”

Application of Perovskite‐Structured Materials in Field‐Effect Transistors

“…[1,2] Hence, the dimensions of FET devices can be further reduced. [2,[6][7][8][9] The dielectric constant of oxide perovskite materials, which were introduced as the FET dielectric layer, is summarized in Figure 3a, and more details about these devices are presented in Table 2.…”

“…[1,2] However, microelectronic devices have limitations when approaching a small dimension in the semiconductor industry caused by quantum mechanical effects, which puts a stop sign in front of the Moore's law. [2,[5][6][7][8][9] Hence, device scaling requires SiO 2 replacement with high dielectric constant oxides, [4,10] hence preventing tunneling currents while retaining the electronic properties of an ultrathin SiO 2 film. [2,[5][6][7][8][9] Hence, device scaling requires SiO 2 replacement with high dielectric constant oxides, [4,10] hence preventing tunneling currents while retaining the electronic properties of an ultrathin SiO 2 film.…”