CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing

Lee, Gyu-Hyeon; Na, Seongmin; Byun, Ilkwon; Min, Dongmoon; Kim, Jangwoo

doi:10.1109/isca52012.2021.00056

Cited by 13 publications

(5 citation statements)

References 35 publications

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“…For instance, refresh operations will reduce the DRAM availability and noise-limited bit-error rates must be acceptable for the application. Reliability and security aspects may also be relevant, such as retention time limitations due to row-hammer attacks [24].…”

Section: Discussionmentioning

confidence: 99%

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A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

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The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-thresholdvoltage (LVT) DRAM at 4.2 K is up to 2× more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 000×, thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

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Section: Discussionmentioning

confidence: 99%

“…Cryogenic memories have been actively explored for (superconducting) high-performance computing [20], [21], [22], [23], [24], [25] and, more recently, for QC applications. From both perspectives, commercial DRAM memories have been investigated down to 77 K [26], [27], [28], [29], [30], [31].…”

Section: Introductionmentioning

confidence: 99%

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

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“…A recent work [194] proposes a new methodology for configuring PPRs. 2) Deterministic preventive refresh (DPR) mechanisms [88,98,101,102,105,107,[110][111][112]117,123,126,131,134,172,195] track activation counts of aggressor rows and preventively refresh victim rows. DPR mechanisms incur less performance overhead than PPR mechanisms (from fewer unnecessary preventive refresh operations) at the cost of larger chip area overhead to store aggressor row activation counters.…”

Section: Related Workmentioning

confidence: 99%

An Experimental Analysis of RowHammer in HBM2 DRAM Chips

Olgun,

Osseiran,

Yağlıkçı

et al. 2023

2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)

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We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening RowHammer vulnerability. We observe that both benign workloads and RowHammer attacks tend to access DRAM rows with the same row address in multiple DRAM banks at around the same time. Based on this observation, ABACuS's key idea is to use a single shared row activation counter to track activations to the rows with the same row address in all DRAM banks. Unlike stateof-the-art RowHammer mitigation mechanisms that implement a separate row activation counter for each DRAM bank, ABA-CuS implements fewer counters (e.g., only one) to track an equal number of aggressor rows.Our comprehensive evaluations show that ABACuS securely prevents RowHammer bitflips at low performance/energy overhead and low area cost. We compare ABACuS to four state-ofthe-art mitigation mechanisms. At a near-future RowHammer threshold of 1000, ABACuS incurs only 0.58% (0.77%) performance and 1.66% (2.12%) DRAM energy overheads, averaged across 62 single-core (8-core) workloads, requiring only 9.47 KiB of storage per DRAM rank. At the RowHammer threshold of 1000, the best prior low-area-cost mitigation mechanism incurs 1.80% higher average performance overhead than ABACuS, while ABACuS requires 2.50× smaller chip area to implement. At a future RowHammer threshold of 125, ABACuS performs very similarly to (within 0.38% of the performance of) the best prior performance-and energy-efficient RowHammer mitigation mechanism while requiring 22.72× smaller chip area. We also show that ABACuS's performance scales well with the number of DRAM banks. At the RowHammer threshold of 125, ABA-CuS incurs 1.58%, 1.50%, and 2.60% performance overheads for 16-, 32-, and 64-bank systems across all 62 single-core workloads, respectively. ABACuS is freely and openly available at https://github.com/CMU-SAFARI/ABACuS.

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“…The liquid nitrogen temperature (77 K) is considered by many researchers to be the most suitable temperature for massive HPC applications, because it balances the performance benefits and cost-effectiveness [3][4][5][6][7][8][9][10]. Example studies include Lee et al's proposed CryoGuard, a robust, near refresh-free DRAM operating at 77 K [8]; Byun et al's 77 K processor architecture, which demonstrated 3.4 times performance improvement [11]. Similarly, TSMC achieved an impressive 70% reduction in SRAM read latency using a 5 nm FinFET process at 77 K [12].…”

Section: Introductionmentioning

confidence: 99%

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

Hu,

Ren,

Yin

et al. 2024

Semicond. Sci. Technol.

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In this work, we systematically investigate the DC performance of Fully Depleted Silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by TCAD simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

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CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing

Cited by 13 publications

References 35 publications

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

An Experimental Analysis of RowHammer in HBM2 DRAM Chips

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

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