Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3–4 nm wide fins and 20 nm gate length for quantum computing applications

Gupta, Sumeet; Rathi, Aarti; Parvais, B.; Dixit, Abhisek

doi:10.1016/j.sse.2021.108089

Cited by 14 publications

(3 citation statements)

References 13 publications

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“…Prior work on 28-nm FD-SOI technology node has reported cryogenic device behavior extensively [8], [9], [10], [11], [12], [13], [14], [15], [16]. Extensive work on the enhancement of industry standard compact models to include the cryogenic temperature effects has also been reported [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29]. The effect of back gate bias towards dc parameter modulation down to cryogenic temperatures was shown in [16], [30], [31].…”

Section: Introductionmentioning

confidence: 99%

Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic Temperatures

Bhardwaj

Singh

Dixit

2023

IEEE J. Electron Devices Soc.

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In this paper, we present on the cryogenic characterization of short channel 28-nm FD-SOI nMOS and pMOS transistors having widths of the 1 μm and 0.08 μm at temperatures ranging from T = 300 K down to T = 10 K. We report, for the first time, the alarming concerns that the narrow-width effect imposes on the overall performance of highly scaled FD-SOI technologies, at temperatures below T = 77 K. The performance comparison between nMOS and pMOS devices is based on their drain current, threshold voltage, transconductance, subthreshold slope, low field mobility and total resistance. Our results show that the sensitivity of narrow width effects towards drain current, threshold voltage and total resistance is smaller in pMOS as compared to nMOS. The effective improvement in transconductance is also significantly larger in narrow width pMOS in comparison to their nMOS counterparts. A substantial degradation of subthreshold swing, total resistance and low field mobility is also observed in narrow nMOS devices, which questions the width scaling benefits of these technologies at cryogenic temperatures.INDEX TERMS Cryogenic temperatures, fully depleted silicon on insulator (FD-SOI), MOSFET, subthreshold slope, cryogenic-CMOS behavior, narrow-width-effect.

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Section: Introductionmentioning

confidence: 99%

Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic Temperatures

Bhardwaj

Singh

Dixit

2023

IEEE J. Electron Devices Soc.

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“…3(c variation of subthreshold swing (𝑆𝑆) over the entire temperature range. It shows that subthreshold swing decreases with decreasing temperature and saturates approximately at 77K, which can possibly be due to the presence of disorder-induced band-tails [1]. Fig.…”

Section: Resultsmentioning

confidence: 87%

“…MOS technology is immensely popular due to its low cost and high integration density. In addition to a multitude of room and high temperature applications, CMOS is also being increasingly considered for cryogenic applications, such as quantum computing, space, and astronomical detectors [1][2][3]. Quantum computing on a CMOS platform is currently attracting a lot of attention.…”

Section: Introductionmentioning

confidence: 99%

Flicker Noise (1/f) in 45-nm PDSOI N-Channel FETs at Cryogenic Temperatures for Quantum Computing Applications

Pathak,

Gupta,

Srinivasan

et al. 2024

IEEE J. Electron Devices Soc.

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In this paper, we have investigated the flicker noise (𝟏 𝒇 ⁄ ) in 45-nm RFSOI NFETs for quantum computing applications. 𝟏 𝒇 ⁄ noise characterization and analysis were performed in linear region at cryogenic temperatures down to 10K. A Lorentzian-like noise is also observed depending on bias conditions, possibly due to the floating body of PDSOI. The extracted frequency exponent (𝜸) shows an inverted U-shape behavior with temperature mainly attributed to non-uniform energy distribution of traps in the gate dielectric. The dominant source of 𝟏 𝒇 ⁄ noise is carrier number fluctuation. Thermalactivation behavior of 𝟏 𝒇 ⁄ noise is studied, which shows the traps responsible for noise are not thermally activated. Volume trap densities are also extracted from 300K down to 10K. The volume trap density increases with a decrease in temperature, but no significant increase in normalized noise is observed at cryogenic temperatures in the measured NFETs. The non-uniform distribution along with the thermal inactive behavior of traps over the studied temperature range is expected to be a plausible reason for the temperature-independent behavior of normalized noise.

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Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

Ghosh,

Nelapati

2023

Silicon

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This article presents the reliability analysis of a High-k stacked Dual Gate Junction-less MOSFET at Deep Cryogenic Temperatures (as low as 50 Kelvin) in terms of dc, analog and RF stability performance metrics. Furthermore, the dc and analog figure of merits in the presence polarized interface trap charge densities has been analyzed at subambient temperatures. The steep ON-OFF switching and the sub-threshold slope profile shows heavy reliance on temperature variations and confirm that the transistor electrostatics improve at lower temperatures. The study reveals the compatibility of the device to perform at cryogenic temperatures and can be integrated with CMOS technology for quantum computations.

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Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3–4 nm wide fins and 20 nm gate length for quantum computing applications

Cited by 14 publications

References 13 publications

Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic Temperatures

Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic Temperatures

Flicker Noise (1/f) in 45-nm PDSOI N-Channel FETs at Cryogenic Temperatures for Quantum Computing Applications

Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

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