Cryogenic surface ion trap based on intrinsic silicon

Niedermayr, Michael; Lakhmanskiy, Kirill; Kumph, Muir; Partel, Stefan; Edlinger, Jonannes; Brownnutt, Michael; Blatt, R.

doi:10.1088/1367-2630/16/11/113068

Cited by 45 publications

(49 citation statements)

References 40 publications

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“…When scaled by 1=d 4 to compare traps of different sizes, this heating rate is lower than that reported in any other trap fabricated on a silicon substrate. 8,9,11,12,14,24 Motional heating at this level would lead to an error of less than 10 À2 in a 100 ls two-ion-qubit gate, below the faulttolerance threshold for large scale quantum computing with surface-code error-correction schemes. 25 We have shown basic functionality for quantum processing using a fabrication process, without modification, that has enabled scaling to billions of transistors.…”

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confidence: 98%

“…The traps are often built upon nonsilicon substrates, 6,7 and where silicon is used, only a few metal layers (four maximum) have been implemented. [8][9][10][11][12][13][14][15] None of the traps made on silicon substrates to date have had doped, active device fabrication available, and due to the idiosyncratic process steps used, the lithographic resolution is typically limited. Repeatability at different facilities is almost impossible due to local process variations and substrate processing capabilities.…”

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confidence: 99%

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Ion traps fabricated in a CMOS foundry

Mehta

Eltony

Bruzewicz

et al. 2014

Applied Physics Letters

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We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.Comment: 4 pages, 3 figure

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confidence: 98%

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confidence: 99%

Ion traps fabricated in a CMOS foundry

Mehta

Eltony

Bruzewicz

et al. 2014

Applied Physics Letters

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“…where S E (ω + ) is the spectral density of electric field [32][33][34][35][36][37][38], squares denote measurements in Penning traps on single ions [21] and ion crystals [39,40] conducted at room temperature. This work is plotted as a blue circle.…”

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confidence: 99%

Measurement of Ultralow Heating Rates of a Single Antiproton in a Cryogenic Penning Trap

et al. 2019

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We report on the first detailed study of motional heating in a cryogenic Penning trap using a single antiproton. Employing the continuous Stern-Gerlach effect we observe cyclotron quantum transition rates of 6(1) quanta/h and an electric field noise spectral density below 7.5(3.4)×10 −20 V 2 m −2 Hz −1 , which corresponds to a scaled noise spectral density below 8.8(4.0) × 10 −12 V 2 m −2 , results which are more than two orders of magnitude smaller than those reported by other ion trap experiments.Quantum control techniques applied to trapped charged particles, well-isolated from environmental influences, have very versatile applications in metrology and quantum information processing. For example, elegant experiments on co-trapped laser cooled ions in Paul traps have provided highly precise state-of-the-art quantum logic clocks [1], enabled the development of exquisite atomic precision sensors [2] and the implementation of quantum information algorithms applied with highly entangled ion-crystals [3]. Decoherence effects from noise driven quantum transitions, commonly referred to as anomalous heating [4,5], affect the scalability of multiion systems, which would enable even more powerful algorithms. Trapped particles are also highly sensitive probes to test fundamental symmetries, and to search for physics beyond the standard model [6,7]. The most precise values of the mass of the electron [8] and the most stringent tests of bound-state quantum electrodynamics [9] are based on precise frequency measurements on highly-charged ions in Penning traps. Measurements of the properties of trapped electrons [10] and positrons [11] provide the most sensitive tests of quantum electrodynamics and of the fundamental charge-parity-time (CPT) invariance in the lepton sector [12,13]. Our experiments [14] make high-precision comparisons of the fundamental properties of protons and antiprotons, and provide stringent tests of CPT invariance in the baryon sector. We recently reported on an improved determination of the proton magnetic moment with a fractional precision of 300 parts in a trillion [16] and the * matthias.joachim.borchert@cern.ch first high-precision determination of the antiproton magnetic moment with a fractional precision of 1.5 parts in a billion [15]. This measurement, based on a newly invented multi-trap method, improves the fractional precision achieved in previous studies [17,18] by more than a factor of 3000. These multi-trap based high-precision magnetic moment measurements on protons and antiprotons require low-noise conditions much more demanding than in any other ion trap experiment. Compared to experiments on electrons and positrons [10,11], the 660fold smaller proton/antiproton magnetic moment makes it much more challenging to apply high-fidelity single particle spin-quantum spectroscopy techniques [19]. Our experiments become possible only in cryogenic ultra-lownoise Penning-trap instruments, which provide energy stabilities of the particle motion on the peV/s range, effectively corresponding to a para...

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“…As shown in figure 12(a), fault tolerance is not achieved above n K 2 25 = / quanta s −1 which corresponds to a motional mode heating rate during the gate (ṅ) of 100 and 200 quanta s −1 for K=2 and K=4, respectively. A heating rate (ṅ) of about 58 quanta s −1 has been observed for a single 9 Be + ion on a room temperature surface trap with a cleaned surface (40 μs above the trap surface, 3.6 MHz trap frequency) [126] and a silicon based trap in a cryogenic environment used to trap individual 40 Ca + ions exhibited heating rates as low as 0.33 quanta s −1 (0.6(2) quanta s −1 on average) (230 μs from the surface, 1.1 MHz trap frequency) [127]. For 171 Yb + ions located 70 μs above the trap surface with a trap frequency of 3 MHz, these heating rates correspond to expected heating rates of 0.5 quanta s −1 and 0.7 quanta s −1 assuming that the heating rate scales as ω −2.4 for fixed ion and d −4 for fixed ω [126,128].…”

Section: Single Error Source Dominant Effectsmentioning

confidence: 99%

Simulating the performance of a distance-3 surface code in a linear ion trap

Trout

Gutiérrez

et al. 2018

New J. Phys.

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We explore the feasibility of implementing a small surface code with 9 data qubits and 8 ancilla qubits, commonly referred to as surface-17, using a linear chain of 171 Yb+ ions. Two-qubit gates can be performed between any two ions in the chain with gate time increasing linearly with ion distance. Measurement of the ion state by fluorescence requires that the ancilla qubits be physically separated from the data qubits to avoid errors on the data due to scattered photons. We minimize the time required to measure one round of stabilizers by optimizing the mapping of the two-dimensional surface code to the linear chain of ions. We develop a physically motivated Pauli error model that allows for fast simulation and captures the key sources of noise in an ion trap quantum computer including gate imperfections and ion heating. Our simulations showed a consistent requirement of a two-qubit gate fidelity of 99.9% for the logical memory to have a better fidelity than physical two-qubit operations. Finally, we perform an analysis of the error subsets from the importance sampling method used to bound the logical error rates to gain insight into which error sources are particularly detrimental to error correction.

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Cryogenic surface ion trap based on intrinsic silicon

Cited by 45 publications

References 40 publications

Ion traps fabricated in a CMOS foundry

Ion traps fabricated in a CMOS foundry

Measurement of Ultralow Heating Rates of a Single Antiproton in a Cryogenic Penning Trap

Simulating the performance of a distance-3 surface code in a linear ion trap

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