Cryogenic computer architecture modeling with memory-side case studies

Lee, Gyu-Hyeon; Min, Dongmoon; Byun, Ilkwon; Kim, Jangwoo

doi:10.1145/3307650.3322219

Cited by 23 publications

(3 citation statements)

References 26 publications

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“…Cryogenic memories have been actively explored for (superconducting) high-performance computing [20], [21], [22], [23], [24], [25] and, more recently, for QC applications. From both perspectives, commercial DRAM memories have been investigated down to 77 K [26], [27], [28], [29], [30], [31].…”

Section: Introductionmentioning

confidence: 99%

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

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The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-thresholdvoltage (LVT) DRAM at 4.2 K is up to 2× more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 000×, thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

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Section: Introductionmentioning

confidence: 99%

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

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“…For DRAM, it has been reported that the data retention characteristics, one of the most important memory performance, are significantly improved at 77 K [8]. For read and write latency, the power consumption and the refresh operation are also improved; then, we are able to apply the cryogenic operation to boost DRAM performance [14], [15]. As one of the emerging memory devices, cryogenic operation of floating body cells (FBC) has been reported [16].…”

Section: Introductionmentioning

confidence: 99%

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

Sanuki¹,

Aiba²,

Tanaka³

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This report introduces the cryogenic operation and storage performance of 3-D flash memory. The cell transistor characteristics and the basic functionalities, including read and program and erase (P/E) operations, are investigated at an extremely low temperature of 77 K cooled by the liquid nitrogen. The cell transistor has a steep subthreshold slope at 77 K compared with at 300 K, and the read operation is fully functional even though the saturation current becomes relatively small. P/E operations at 77 K are not much different from those at 300 K, and the same incremental-step pulse programming (ISPP) and incremental-step pulse erase (ISPE) methods are applicable. In addition, the storage performance and the reliability characteristics of 3-D flash memory, such as the read noise, the disturb characteristics, the data retention, and the cycle endurance, are also investigated. While there is no degradation in the disturb characteristics, the read noise at 77 K was significantly minimized compared with that at 300 K. The data retention characteristics are about three times improved, and the cycle endurance is about ten times improved at 77 K compared with at 300 K. These storage performance improvements and high-reliability characteristics at cryogenic operation enable us to achieve the ultramultilevel cell. We show the successful demonstration of 6-bit per cell (HLC) and discuss the impact of additional cooling cost and the possibility of future storage devices beyond HLC. The cryogenic operation of 3-D flash memory can greatly improve the storage performance and opens the door for potential new applications and the bit cost scaling for future storage devices.INDEX TERMS 3-D flash memory, 6-bit per cell (HLC), 77 K, bit cost scaling, cryogenic, immersion cooling, liquid nitrogen, NAND.

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“…Moreover, the memory capacity of the on-chip cache is dependent on the physical space of the semiconductor chip. The insufficient capacity of on-chip cache memories and bandwidth of off-chip memory have been major problems of modern computer architecture [51]- [56]. Thus, off-chip fast memory that has larger memory capacity is required so that large data such as lookup tables for virtualized carrier network functions can be accommodated.…”

Section: Introductionmentioning

confidence: 99%

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Korikawa

Kawabata

et al. 2020

IEEE Access

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Packet processing performance of Network Function Virtualization (NFV)-aware environment depends on the memory access performance of commercial-off-the-shelf (COTS) hardware systems. Table lookup is a typical example of packet processing, which has a significant dependence on memory access performance. Thus, the on-chip cache memories of the CPU are becoming more and more critical for many high-performance software routers or switches. Moreover, in the carrier network, multiple applications run on top of the same hardware system in parallel, which requires the capacity of cache memories. In this paper, we propose a packet processing architecture that enhances memory access parallelism by combining on-chip last-level-cache (LLC) slices and off-chip interleaved 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) devices. Table entries are stored in the off-chip 3D-stacked DRAM, so that memory requests are processed in parallel by using bank interleaving and channel parallelism. Also, cached entries are distributed to on-chip LLC slices according to a memory address-based hash function so that each CPU core can access on-chip LLC in parallel. The evaluation results show that the proposed architecture reduces the memory access latency by 62 % and 12 % and increases the throughput by 108 % and 2 % with reducing blocking probability of memory requests 96 % and 50 %, compared to the architecture with on-chip shared LLC and that without on-chip LLC, respectively.

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Cryogenic computer architecture modeling with memory-side case studies

Cited by 23 publications

References 26 publications

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

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