Crosstalk constrained global route embedding

Parakh, Phiroze N.; Brown, Richard B.

doi:10.1145/299996.300077

Cited by 11 publications

(5 citation statements)

References 8 publications

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“…Only a limited number of works have considered these effects at the global routing level [Parakh andBrown, 1999, Zhou andWong, 1998]. However, the incorporation of these effects is mostly performed at the detailed routing level.…”

Section: Incorporating Crosstalk and Parasitics Into Routingmentioning

confidence: 99%

Mixed-Signal Layout Generation Concepts

Roermund¹,

Leenaerts²

2005

The International Series in Engineering and Computer Science

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PrefaceLayout generation is an important topic in IC design. For digital circuits a lot of research has been conducted in this area, resulting in a large variety of books and layout generation tools. However, with the ever increasing frequencies, we are facing now significant analog types of artifacts in the IC, introduced during the physical design phase, when schematics are translated to physical ICs via a layout. Moreover, with the trend to systems on chip, analog circuitry and massive amounts of digital circuitry are going to be integrated on the same chip, now called a mixed-signal chip. Compatibility between the high-resolution but low-level analog signals and the relatively large-swing digital signals with their fast transition edges is becoming a severe problem, which makes layout generation a tedious and complex job.In this book we focus on two strongly coupled aspects of automatic layout generation, placement and routing. We will discuss the problem in detail in the context of mixed-signal designs. Apart from the physical artifacts and their parasitic influence on the electrical behaviour of the circuit, we will address aspects related to the optimization problem associated with automatic layout generation. These are the optimization methods, with special emphasis on simulated annealing; adequate data structures; appropriate models and representations; and efficient algorithms. As optimization is an iterative process, incremental algorithms that only generate strictly necessary new information are especially interesting to speed up the process. These algorithms get special attention.The book can be seen as a combination of introductory texts and results of new research. Therefore it will be interesting for designers that like to get an overall picture, and for experts in the field who like to see the state of the art, and who will be interested in the new topics discussed in this book. Moreover, it is interesting both for designers and specialists in the area of circuit design and for those working in the area of electronic design automation (EDA).From the new contributions we will mention only a few selected issues here. A novel incremental approach to placement optimization is presented, featuring significantly improved asymptotic computational complexity results for a single placement computation within a simulated-annealing environment. A new consistent linear-time algorithm is described that maps a given placement of modules in a user-specified region to an efficient formal representation, such that the information can be further processed by means of efficient algorithms. Efficiency is an important issue for CAD tools. An improved robust placement algorithm is addressed. The algorithm can incorporate range and boundary constraints that are imposed on specific modules in a very efficient manner. Further, a framework is given that incorporates placement and routing, making it easy to take into account physical problems that are related to the spatial distribution of objects in a plane, which in this...

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Section: Incorporating Crosstalk and Parasitics Into Routingmentioning

confidence: 99%

Mixed-Signal Layout Generation Concepts

Roermund¹,

Leenaerts²

2005

The International Series in Engineering and Computer Science

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“…The typical strength of coupled signals for a differential on-chip VCO topology, with integrated inductors and varactors was determined. Equivalent integral form,[4][5]23 Fanin,38 Fanout,17,[38][39][40]112,129 Fast cosine transform (FCT), 30 Fast Fourier Transform (FFT), 28,30 Feedback,[85][86][87]93,97,133 Fingerprints,35 Finite difference method, 5-6, 28, 36, 61 Finite element method, 5, 28 Floorplan of the VCO, 56 Floorplanning, 34, 61 Frequency dividers, 6, 50 Frequency-pulling, 95 Fringing fields, 99-100, 109 Glitch transients, 17 GMRES, 29-30 Gradient based method, 63 Green's function, [23][24][25][26][27]30,35,47,65,67,81,137 Guard ring layout,112 Guard ring,12,16,34,50,65,87,112,115,117,119,121, [33][34]38 Substrate noise sources, 89 Substrate noise, [1][2][3]5,…”

Section: Frequency Domain Measurementsmentioning

confidence: 99%

Substrate Noise

2003

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“…A tremendous amount of work has been reported on either timing driven interconnect routing [1][2][3] or coupling noise avoidance [4][5][6][7][8][9][10][11][12][13][14]. However, very few works address the closely related timing and coupling issue at the same time.…”

Section: Introductionmentioning

confidence: 99%

Timing driven track routing considering coupling capacitance

Zhao

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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Abstract-As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven routing. In this paper, a coupling aware timing driven track routing heuristic is proposed. Given a global routing solution and timing constraint for each net, major trunks of wire segments are assigned to routing tracks such that the minimum timing slack among all nets is maximized. Delay penalties from both coupling capacitance and wire detour are considered in a unified graph model. The core problem is formulated and solved as a Sequential Ordering Problem (SOP). Routing blockages are handled in a post processing procedure. The experimental results on benchmark circuits show that the effect of coupling capacitance on timing is significant and the proposed heuristic results in greater improvement on coupling aware timing compared with other approaches.

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Crosstalk constrained global route embedding

Cited by 11 publications

References 8 publications

Mixed-Signal Layout Generation Concepts

Mixed-Signal Layout Generation Concepts

Substrate Noise

Timing driven track routing considering coupling capacitance

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