Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip

Abstract

Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number of wires. In addition, it has small penalty on the network performance, represented by the average latency and comparable codec area overhead to other schemes.

Crosstalk Aware Multi-Bit Error Detection with Limited Error Correction Coding for Reliable On-Chip Communication

“…Since any flit may be retransmitted one or more times, then it is required to find the average number of flit transmissions required to be successfully accepted by the decoder, T. This average number includes the probability to be accepted in the first transmission, or after one or more retransmissions, as given by [14,15]:…”

“…The latter was enhanced in [13] to provide lower power consumption at lower noise levels. The authors in [14] proposed a new joint scheme providing seven errors detection at the cost of no error correction. The absence of error correction negatively affects performance due to the high number of retransmissions at high bit error rates.…”

“…This paper argues that it is possible to modify JTEC-SQED to provide higher detection while limiting its correction capability to single errors. Although it is theoretically possible to provide seven errors detection using the same redundancy, this may lead to high retransmission rate as in [14] due to the absence of error correction. In addition, the adaptivity provided in [13] can also be applied to the new proposed scheme.…”

Recent trends and considerations for high speed data in chips and system interconnects

“…However, given the inherent difficulty of decoding multi-bit error correction, the works of [55][56] combine single error correction with ARQ techniques for NoC interconnects. This solution, although also it is able of ensuring the reliability of the transmitted data as well augments the bus size and so the area to integrate raise.…”

Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip

“…The lack of crosstalk delay reduction in the first group and the error protection in the second motivated the development of new coding schemes [23,[29][30][31][32][33][34][35][36] that address these shortcomings. These codes mainly join a crosstalk avoidance code with an error detection/correction code to achieve their dual goal.…”