Crosscoupling power optimal wire spacing in quasilinear runtime

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

“…Additionally, as reported in Ref. [9], that 95% of signals in a highend microprocessor have switching factors less than 0.2 guarantees the application scope of this optimization method.…”

“…Using the characteristic of values transmitted over the data bus, an encoding scheme called the FV encoding scheme was developed. [8] Zuber et al [9] developed a new quasilinear algorithm for solving the coupling power optimal wire spacing problem and, later, according to non-uniform wire spacing, they [2] proposed a routing optimization method for low interconnect dynamic power. In addition, optimal ordering was proposed by Zuber et al [10] to enhance the effect of power optimal wire spacing.…”

Wire Topology Optimization for Low Power CMOS

“…In that case, both capacitance components are switched with different effective activities. It was shown in [13] that the power prediction error for typical examples of bus wires can reach 10%-20% if 100% of the wires switch simultaneously and are correlated. In a flatly routed design, however, we find by static timing analysis that actually only a (pessimistic) fraction of about 10% of all nets exhibit timing windows that overlap with neighboring nets.…”