Crossbar RRAM Arrays: Selector Device Requirements During Write Operation

Zhou, Jian; Kim, Kuk-Hwan; Lü, Wei

doi:10.1109/ted.2014.2327514

Cited by 139 publications

(27 citation statements)

References 11 publications

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“…Considering only a single synaptic device, the demonstrated synaptic transistor in this study may require more energy consumption compared to existing memristors. However, considering the large-scale array of synaptic devices, the energy consumption from the sneaky-current flow will be more critical 37 . However, the existing memristors cannot prevent this problem completely without introducing an additional selector device.…”

Section: Resultsmentioning

confidence: 99%

Binarized Neural Network with Silicon Nanosheet Synaptic Transistors for Supervised Pattern Classification

Kim

Choi

Yoon

et al. 2019

Sci Rep

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In the biological neural network, the learning process is achieved through massively parallel synaptic connections between neurons that can be adjusted in an analog manner. Recent developments in emerging synaptic devices and their networks can emulate the functionality of a biological neural network, which will be the fundamental building block for a neuromorphic computing architecture. However, on-chip implementation of a large-scale artificial neural network is still very challenging due to unreliable analog weight modulation in current synaptic device technology. Here, we demonstrate a binarized neural network (BNN) based on a gate-all-around silicon nanosheet synaptic transistor, where reliable digital-type weight modulation can contribute to improve the sustainability of the entire network. BNN is applied to three proof-of-concept examples: (1) handwritten digit classification (MNIST dataset), (2) face image classification (Yale dataset), and (3) experimental 3 × 3 binary pattern classifications using an integrated synaptic transistor network (total 9 × 9 × 2 162 cells) through a supervised online training procedure. The results consolidate the feasibility of binarized neural networks and pave the way toward building a reliable and large-scale artificial neural network by using more advanced conventional digital device technologies.

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Section: Resultsmentioning

confidence: 99%

Binarized Neural Network with Silicon Nanosheet Synaptic Transistors for Supervised Pattern Classification

Kim

Choi

Yoon

et al. 2019

Sci Rep

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“…The worst-case scenario involves selecting the cell that is located at the furthest corner from the voltage source and ground, due to the finite WL and BL resistance. In our simulations, the sense margin is calculated using the change in voltage dropped across the sense resistor between scenarios 8 and 9 [16,22].…”

Section: Methodsmentioning

confidence: 99%

Modelling resistive and phase-change memory with passive selector arrays: a MATLAB tool

Noori

Groot

2020

J Comput Electron

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Memristor devices are crucial for developing neuromorphic computers and next-generation memory technologies. In this work, we provide a comprehensive modelling tool for simulating static DC reading operations of memristor crossbar arrays that use passive selectors with matrix algebra in MATLAB. The software tool was parallel coded and optimised to run with personal computers and distributed computer clusters with minimised CPU and memory consumption. We study the effect of changing the line resistance, array size, voltage selection scheme, selector diode's ideality factor, reverse saturation current and sense resistance on the electrical behaviour and expected sense margin of a conventional one-diode-one-resistor crossbar arrays. We then investigate the effect of single-and dual-side array biasing and grounding on the dissipated current throughout the array cells. The tool we offer to the memristor community and the studies we present enable the design of larger and more practical memristor arrays for application in data storage and neuromorphic computing.

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“…To face this issue, the bias voltage applied to the WL could be increased, but this results in increasing power demand and increasing Joule dissipation, hence increasing temperature. Other proposed solutions are based on advanced bias schemes, such as, for instance, the 1/3 bias scheme that enables a larger read margin or the 1/2 one that leads to a lower power consumption [14], [15]. However, signal integrity analysis disregarded the coupled electrothermal effects.…”

Section: Introductionmentioning

confidence: 99%

Signal and Thermal Integrity Analysis of 3-D Stacked Resistive Random Access Memories

Zayer

Lahbacha

Melnikov

et al. 2021

IEEE Trans. Electron Devices

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In this article, a 3-D electrothermal numerical model is used to perform the signal and thermal integrity analysis of 3-D stacked Resistive-switching random access memory (RRAM) arrays. Two main issues are found: voltage drop along the interconnects and thermal crosstalk between the memory cells. Possible solutions to these issues are here thoroughly investigated, based either on new biasing schemes or new materials. Especially, conventional nickel bars are replaced by interconnects made by copper (Cu) and carbon nanotubes (CNTs), whose electrical and thermal parameters are here described using physically based models. The analysis is performed on a 5 × 5 × 5 array, under a real case of a RESET switching, which is the worst case scenario from the electrothermal point of view. Simulation results show that the use of CNTs reduces the voltage drop in both word and bitline (BL) interconnects, thermal crosstalk, and the maximum working temperature; hence, it mitigates many of the crucial issues in the roadmap for the large-scale monolithic 3-D RRAM integration.

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Crossbar RRAM Arrays: Selector Device Requirements During Write Operation

Cited by 139 publications

References 11 publications

Binarized Neural Network with Silicon Nanosheet Synaptic Transistors for Supervised Pattern Classification

Binarized Neural Network with Silicon Nanosheet Synaptic Transistors for Supervised Pattern Classification

Modelling resistive and phase-change memory with passive selector arrays: a MATLAB tool

Signal and Thermal Integrity Analysis of 3-D Stacked Resistive Random Access Memories

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