2005
DOI: 10.1016/j.sse.2005.07.008
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Cross-talk suppression in SOI substrates

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Cited by 11 publications
(7 citation statements)
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“…This is a significant problem when a material with a very low doping concentration is used ͑e.g., FZ͒ as the inversion layer reduces the effective substrate resistance. 17 Gold ͑Au͒ doping has been reported to produce high resistivity silicon by other workers 18 who observed a maximum resistivity of 100 k⍀ cm. They also used a low pressure chemical vapor deposition ͑LPCVD͒ silicon nitride diffusion barrier to prevent the Au atoms from diffusing to the active layer.…”
Section: The Fabrication Of Si-si Substratesmentioning
confidence: 96%
See 1 more Smart Citation
“…This is a significant problem when a material with a very low doping concentration is used ͑e.g., FZ͒ as the inversion layer reduces the effective substrate resistance. 17 Gold ͑Au͒ doping has been reported to produce high resistivity silicon by other workers 18 who observed a maximum resistivity of 100 k⍀ cm. They also used a low pressure chemical vapor deposition ͑LPCVD͒ silicon nitride diffusion barrier to prevent the Au atoms from diffusing to the active layer.…”
Section: The Fabrication Of Si-si Substratesmentioning
confidence: 96%
“…This value of 3.7 ϫ 10 −13 cm 2 s −1 at 1000°C compares well to the only other diffusivity in the literature for LPCVD Si 3 N 4 , which is 3.2 ϫ 10 −13 cm 2 s −1 at the same temperature. 17 Silicon dioxide diffusion barrier.-DLTS spectra were taken from Schottky contacts fabricated on the bottom wafer separated from the Au source by a BOX layer, as in Fig. 4.…”
Section: H542mentioning
confidence: 99%
“…It should be noted that the pinning of the Fermi level in this way will prevent the production of an inversion layer that is sometimes produced in SOI wafers. This is a significant problem as the inversion layer reduces the effective substrate resistance in high resistivity silicon substrates with low background doping and can be a particular problem when FZ material is used in this role [14].…”
Section: Impurity Doping: the Role Of Deep Energy Levelsmentioning
confidence: 99%
“…Due to the large number of grain boundaries and defects in polysilicon, it can effectively trap free carriers caused by the PSC effect, it is also compatible with mature integrated circuit (IC) manufacturing processes and has very good thermal stability [ 12 ]. Therefore, the PSC effect on HR-Si substrate can be effectively suppressed by the polysilicon carrier trap layer, and can further improve the RF performance of the substrate [ 13 ]. This method is currently widely used to eliminate the PSC effect on HR-Si on insulator (HR-SOI) substrates.…”
Section: Introductionmentioning
confidence: 99%