Optical Microlithography XXXI 2018
DOI: 10.1117/12.2297387
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Cross-platform (NXE-NXT) machine-to-machine overlay matching supporting next node chip manufacturing

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Cited by 3 publications
(4 citation statements)
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“…In general, a 300 mm wafer was used in the EUV process, and the maximum size of a die was 26 × 33 mm 2 . [6][7][8] The overall schematic diagram of the simulation is illustrated in Fig. 1.…”
Section: Modeling Processmentioning
confidence: 99%
See 1 more Smart Citation
“…In general, a 300 mm wafer was used in the EUV process, and the maximum size of a die was 26 × 33 mm 2 . [6][7][8] The overall schematic diagram of the simulation is illustrated in Fig. 1.…”
Section: Modeling Processmentioning
confidence: 99%
“…Current overlay accuracy of the ASML's NXE series scanner is known to be 1.1 nm, and the target CD is continuously decreasing. 7) Therefore, it is necessary to quantitatively analyze the overlay error due to thermal deformation and apply the corresponding correction to the EUV mask design. This study focused on analyzing the thermo-mechanical problems that directly affect the overlay and LCDU.…”
Section: Introductionmentioning
confidence: 99%
“…Consequently, the increase of lens reduction from 4× to 8× on high-NA EUV exposure tools means that the mask must scan during exposures at twice the speed of masks on 0.33 NA systems in order to achieve the same wafer scan speed. Wafer scan speeds on EUV exposure tools are currently limited by exposure source power, so they are typically less than the ⩾ 800 mm s −1 achieved on optical exposure tools, 17) but mask scan speeds of multiple meters per second are still required. This must be achieved while meeting the subnanometer position control required for good overlay and imaging.…”
Section: The Key Characteristics Of High-na Euv Lithographymentioning
confidence: 99%
“…The most recent low-NA extreme ultraviolet (EUV) scanners accomplish a matched machine overlay (MMO) of 1.1 nm, and the high-NA EUV scanner aims to meet a specification of 0.8 nm. [1][2] These highly constrained overlay error budgets necessitate the consideration of sub-nano-level thermal deformation induced by EUV exposure. To date, process have been accomplished by mitigating in-plane distortion (IPD) and out-of-plane distortion (OPD) through the regulation of wafer stage cooling and the utilization of a chuck for wafer flatness control.…”
Section: Introductionmentioning
confidence: 99%