Cross link insertion for improving tolerance to variations in clock network synthesis

Mittal, Tarun; Koh, Cheng-Kok

doi:10.1145/1960397.1960407

Cited by 28 publications

(49 citation statements)

References 14 publications

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“…These methods are later extended to handle buffered clock trees in [17], [25]. While most crosslink insertion techniques do not seem competitive with best tree-tuning approaches, a recent cross-link scheme proposed in [13] achieves low overall capacitance by inserting cross links between internal nodes of a clock tree to reduce the total crosslink length. However, these resulting networks use unique, large two-level buffers (10+40 inverters) that seem responsible for the improvement but are not adequately modeled by the ISPD 2010 contest infrastructure.…”

Section: Cross-linksmentioning

confidence: 99%

“…These deficiencies encourage unrealistic clock-network configurations. To this end, the best published results for the ISPD 2010 benchmarks [13] seem to require the stacking of numerous inverters in a unique 10+40 configuration. The authors attribute the quality of results to a new cross-link insertion technique, but do not report results without cross-link insertion to substantiate this claim.…”

Section: A Experiments Designmentioning

confidence: 99%

“…Surprisingly, none of these techniques were useful at the ISPD 2009-2010 clock-network contests [22], [23] despite diligent attempts, as improved tree-tuning methods were sufficient. Careful experiments and analytical estimates [13] have shown that direct cross-links are only effective in poorly tuned clock trees and/or at relatively short distances. However, in high-quality clock trees it is rare to find a critical pair of sinks at a short distance.…”

mentioning

confidence: 99%

“…However, in high-quality clock trees it is rare to find a critical pair of sinks at a short distance. A recent proposal [13] suggests adding cross-links higher in the tree to connect entire branches. As several other publications with strong empirical results, [13] uses unrealistically large composite buffers, and arranges them in a unique two-layer configuration (10+40 small inverters).…”

mentioning

confidence: 99%

“…A recent proposal [13] suggests adding cross-links higher in the tree to connect entire branches. As several other publications with strong empirical results, [13] uses unrealistically large composite buffers, and arranges them in a unique two-layer configuration (10+40 small inverters). Given that the ISPD 2010 contest infrastructure does not adequately model such configurations, the competitiveness of cross-links in practice remains unclear.…”

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confidence: 99%

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Multilevel tree fusion for robust clock networks

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Recent improvements in clock-tree and mesh-based topologies maintain a healthy competition between the two. Trees require much smaller capacitance, but meshes are naturally robust against process variation and can accommodate late design changes. Cross-link insertion has been advocated to make trees more robust, but is limited in practice to short distances. In this work we develop a novel non-tree topology that fuses several clock trees to create large-scale redundancy in a clock network. Empirical validation shows that our novel clock-network structure incrementally enhances robustness to satisfy given variation constraints. Our implementation called Contango3.0 produces robust clock networks even for challenging skew limits, without parallel buffering used by other implementations. It also offers a fine trade-off between power and robustness, increasing the capacitance of the initial tree by less than 60%, which results in 2.3× greater power efficiency than mesh structures.

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Section: Cross-linksmentioning

confidence: 99%

Section: A Experiments Designmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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confidence: 99%

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Multilevel tree fusion for robust clock networks

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Optimal gate sizing using a self-tuning multi-objective framework

et al. 2014

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Synthesis and exploration of clock spines

Kim

2018

IET Computers & Digital Techniques

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This study addresses the problem of developing a synthesis algorithm for clock spine networks, which is able to systematically explore the clock resources and clock variation tolerance. The idea is to transform the problem of allocating and placing clock spines on a plane into a slicing floorplan optimisation (SFO) problem, in which every candidate of clock spine network structures is uniquely expressed into a postfix notation to enable a fast cost computation in the SFO. As a result, the authors proposed synthesis algorithm can explore the diverse structures of the clock spine network to find globally optimal ones within acceptable run time. Through experiments with benchmark circuits, it is shown that the proposed algorithm is able to synthesise the clock spine networks with 38% reduced clock skew over the clock tree structures, even 11% reduced clock power. In addition, in comparison with the clock mesh structures, the proposed clock spine networks have comparable tolerance to clock skew variation while using considerably less clock resources, reducing clock power by 36%.

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Cross link insertion for improving tolerance to variations in clock network synthesis

Cited by 28 publications

References 14 publications

Multilevel tree fusion for robust clock networks

Multilevel tree fusion for robust clock networks

Optimal gate sizing using a self-tuning multi-objective framework

Synthesis and exploration of clock spines

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