Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems

Hassan, Mohamed; Patel, Hiren

doi:10.1109/rtas.2016.7461327

Cited by 34 publications

(21 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Their approach attempts to allow as much parallelism as possible, commensurate with the high-criticality tasks retaining their temporal validity. Hassan and Patel [2016] claim an improved bus arbitrator, called Carb, that is more criticality aware. Bounding the interference that a safety-critical task can suffer from lower criticality tasks using the same shared communication resources on a multi-core platform is also addressed by Nowotsch et al [2014].…”

Section: Communication and Other Resourcesmentioning

confidence: 99%

A Survey of Research into Mixed Criticality Systems

2017

View full text Add to dashboard Cite

This survey covers research into mixed criticality systems that has been published since Vestal's seminal paper in 2007, up until the end of 2016. The survey is organised along the lines of the major research areas within this topic. These include single processor analysis (including fixed priority and EDF scheduling, shared resources and static and synchronous scheduling), multiprocessor analysis, realistic models, and systems issues. The survey also explores the relationship between research into mixed criticality systems and other topics such as hard and soft time constraints, fault tolerant scheduling, hierarchical scheduling, cyber physical systems, probabilistic real-time systems, and industrial safety standards. CCS Concepts: •Computer systems organization → Real-time system specification; •Software and its engineering → Real-time schedulability; Real-time systems software;

show abstract

Section: Communication and Other Resourcesmentioning

confidence: 99%

A Survey of Research into Mixed Criticality Systems

2017

View full text Add to dashboard Cite

show abstract

“…Hassan and Patel 27 introduced CArb, a con¯gurable arbiter of criticality and requirement awareness for dominating accesses to shared memories and buses in multicore MC systems. CArb employs two-tier WRR 77 arbitration to manage these accesses.…”

Section: Qos-oriented Techniques In MC Systemsmentioning

confidence: 99%

A Review of Recent Techniques in Mixed-Criticality Systems

Chai

Zhang

Sun

et al. 2019

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

Unlike traditional embedded systems that almost have only one criticality level, many complex embedded systems nowadays are mixed-critical and are more and more widely used. There has been a lot of research on mixed-criticality (MC) systems. In this paper, we present a survey on the MC systems on these research. First, we discuss the exaltation of the schedulability of MC systems. As improving schedulability may lead to quality-of-service (QoS) reduction of MS systems. Therefore, we investigate the approaches to solve this problem. Improving QoS of MS systems may inevitably increase the energy consumption. Then, we introduce the researches that take the energy efficiency as a design requirement of MC systems. Few MC systems regard fault-tolerance as the design requirement, thus, we extensively investigate fault-tolerance of MC systems. In addition, we introduce some of the main applications for MC systems.

show abstract

“…Accordingly, upon switching to the degraded mode, instead of abandoning them, their guarantees are only degraded. Another approach is followed by [12], where instead of directly switching the mode and suspending lower-critical tasks, the memory service guarantees of those tasks are degraded to reduce the interference on the highercritical to accommodate for the increase in the execution time. These approaches consider a system-wide mode switch, where all the system components and tasks migrate to the new mode.…”

Section: Issues With the Current Modelmentioning

confidence: 99%

“…There exist proposals to address this interference in multi-core MCS at the interconnect (e.g. [12], [15]), the shared cache (e.g. [18], [19]), and the shared DRAM (e.g.…”

Section: Shared Resources: Timing Interferencementioning

confidence: 99%

Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities

Hassan¹

2018

IEEE Des. Test

Self Cite

View full text Add to dashboard Cite

Abstract-Due to their cost, performance, area, and energy efficiency, MPSoCs offer appealing architecture for emerging mixed criticality systems (MCS) such as driverless cars, smart power grids, and healthcare devices. Furthermore, heterogeneity of MPSoCs presents exceptional opportunities to satisfy the conflicting requirements of MCS. Seizing these opportunities is unattainable without addressing the associated challenges. We focus on four aspects of MCS that we believe are of most importance upon adopting MPSoCs: theoretical model, interference, data sharing, and security. We outline existing solutions, highlight the necessary considerations for MPSoCs including both opportunities they create and research directions yet to be explored.

show abstract

Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems

Cited by 34 publications

References 21 publications

A Survey of Research into Mixed Criticality Systems

A Survey of Research into Mixed Criticality Systems

A Review of Recent Techniques in Mixed-Criticality Systems

Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities

Contact Info

Product

Resources

About