Critical path selection for performance optimization

Chen, H.-C.; Du, David H. C.; Liu, L.-R.

doi:10.1109/43.205000

Cited by 42 publications

(13 citation statements)

References 12 publications

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“…Linear reductions model, for example, physical performance optimizations of circuits through w x gate resizing and buffer insertions 1,3,7,8 . Such optimizations do not change the topology of the circuit and result in circuits having a smaller delay.…”

Section: D¨¨g0 R I Jmentioning

confidence: 99%

Edge Weight Reduction Problems in Directed Acyclic Graphs

Hambrusch

1997

Journal of Algorithms

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Let G be a weighted directed acyclic graph in which edge weights are not static quantities, but can be reduced for a certain cost. In this paper we consider the problem of determining which edges to reduce so that the length of the longest paths is minimized and the total cost associated with the reductions does not exceed a given cost. We consider two types of edge reductions, linear reductions and 0r1 reductions, which model different applications. We present efficient algorithms for different classes of graphs, including trees, series᎐parallel graphs, and directed acyclic graphs, and we show other edge reduction problems to be NP-hard. ᮊ 1997 Academic Press

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Section: D¨¨g0 R I Jmentioning

confidence: 99%

Edge Weight Reduction Problems in Directed Acyclic Graphs

Hambrusch

1997

Journal of Algorithms

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“…Current path optimization tools [8] require large CPU times and too significant calculation computer resources to manage the complexity of nowadays developed circuits [9]. The uncertainty in parasitic capacitance estimation imposes to use many iterations or to consider very large safety margin resulting in oversized circuits.…”

Section: Optimization Protocolmentioning

confidence: 99%

Performance Metric Based Optimization Protocol

Michel

Verle

Maurine

et al. 2004

Lecture Notes in Computer Science

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Optimizing digital designs implies a selection of circuit implementation based on different cost criteria. Post-processing methods such as transistor sizing, buffer insertion or logic transformation can be used for optimizing critical paths to satisfy timing constraints. However most optimization tools are not able to select between the different optimization alternatives and have high CPU execution time.In this paper, we propose an optimization protocol based on metrics allowing to characterize a path and to select the best optimization alternative. We define a way to characterize the design space of any circuit implementation. Then we propose a constraint distribution method allowing constraint satisfaction at nearly minimum area. This quasi optimal tool is implemented in an optimization tool (POPS) and validated by comparing the area necessary to satisfy delay constraints applied to various benchmarks (ISCAS'85) to that resulting from an industrial tool.

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“…As a result, the switching delay of a gate can be expressed as a linear combination of step responses of the controlling and switching structures. Each step response can be evaluated from the ratio: (2) where 8. V is the output voltage variation used to evaluate the step response and I the maximum current available in the structure to charge or discharge the output.…”

Section: Modelingmentioning

confidence: 99%

“…Great interest [1][2][3][4] has been given to the research of optimal solutions to the problem of transistor sizing under delay constraint. But very few information is available on the direct determination of bounds on delay [5] allowing to evaluate the feasibility of constraints and/or the efficiency of an implementation.…”

Section: Introductionmentioning

confidence: 99%

Feasible delay bound definition

Azémard

Aline

Maurine

et al. 2002

IFIP Advances in Information and Communication Technology

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Abstract:Minimizing the number of iterations when satisfying performance constraints in Ie design is of fundamental importance to limit the design iterations. We present a method to determine the feasibility of delay constraint imposed on circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinatorial paths. Then we characterise these bounds and present a method to determine, , the average weighted loading factor allowing to satisfy the delay constraint.Example of application is given on different ISeAS circuits.

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Critical path selection for performance optimization

Cited by 42 publications

References 12 publications

Edge Weight Reduction Problems in Directed Acyclic Graphs

Edge Weight Reduction Problems in Directed Acyclic Graphs

Performance Metric Based Optimization Protocol

Feasible delay bound definition

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