Critical issues regarding HPS, a high performance microarchitecture

Patt, Yale N.; Melvin, Stephen; Hwu, Wen mei; Shebanow, Michael

doi:10.1145/18927.18917

Cited by 42 publications

(8 citation statements)

References 2 publications

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“…In particular we consider an organization where an address-based scheduler is used to compare the addresses of loads and stores and to guide load execution. Patt, Melvin, Hwu and Shebanow have also considered some of the tradeoffs involved in using addressbased scheduling in dynamically-scheduled high-performance micro-architectures [22].…”

Section: Using Address-based Schedulingmentioning

confidence: 99%

Memory dependence speculation tradeoffs in centralized, continuous-window superscalar processors

Moshovos

Sohi

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)

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We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work has also investigated such methods [19,4], this has been done primarily for split, distributed window processor models. We focus on centralized, continuous-window processor models (the common configuration today). We confirm that exploiting load/ store parallelism can greatly improve performance. Moreover, we show that much of this performance potential can be captured if addresses of the memory locations accessed by both loads and stores can be used to schedule loads. However, using addresses to schedule load execution may not always be an option due to complexity, latency, and cost considerations. For this reason, we also consider configurations that use just memory dependence speculation to guide load execution. We consider a variety of methods and show that speculation/synchronization can be used to effectively exploit virtually all load/store parallelism. We demonstrate that this technique is competitive to or better than the one that uses addresses for scheduling loads. We conclude by discussing why our findings differ, in part, from those reported for split, distributed window processor models.

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Section: Using Address-based Schedulingmentioning

confidence: 99%

Memory dependence speculation tradeoffs in centralized, continuous-window superscalar processors

Moshovos

Sohi

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)

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“…Load Buffers: Load buffers were initially proposed to temporarily hold loads while older stores were completing, enabling later non-memory operations to proceed [24]. Later, more aggressive out-of-order processors-such as IBM's Power4 [29] and Alpha 21264 [1]-permitted loads to access the data cache speculatively, even with older stores waiting to issue.…”

Section: Historical Memory Ordering Hardwarementioning

confidence: 99%

Scalable hardware memory disambiguation for high-ILP processors

et al. 2004

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“…The key differences of the dependence-based architecture are (i) the register file is not separated into local and global files, and (ii) register renaming information is not reused, thus having the same instruction dispatch rate as traditional superscalar processors. The Multiscalar architecture [Fra92b,Fra93a] Pat85b] ). Static, compiletime partial renaming of individual basic blocks has been proposed in [Spr94a].…”

Section: Previous Workmentioning

confidence: 99%