Critical issues regarding HPS, a high performance microarchitecture

Patt, Yale N.; Melvin, Stephen; Hwu, Wen mei; Shebanow, Michael

doi:10.1145/18906.18917

Cited by 17 publications

(3 citation statements)

References 2 publications

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“…In the first, there is a physical register file larger than the logical register file. A mapping table is used to associate a physical register with the current value of a logical register [21], [30], [45], [46]. Instructions are decoded and register renaming is performed in sequential program order.…”

Section: B Instruction Decoding Renaming and Dispatchmentioning

confidence: 99%

The microarchitecture of superscalar processors

1995

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Superscalar processing is the latest in a long series of innovations aimed at producing everyaster microprocessors. By exploiting instruction-level parallelism, superscalar processors are capable of executing more than one instruction in a clock cycle. This paper discusses the microarchitecture of superscalar processors. We begin with a discussion of the general problem solved by superscalar processors: converting an ostensibly sequential program into a more parallel one. The principles underlying this process, and the constraints that must be met, are discussed. The paper then provides a description of the speciJic implementation techniques used in the important phases of superscalar processing. The major phases include: 1 ) instruction fetching and conditional branch processing, 2 ) the determination of data dependences involving register values, 3) the initiation, or issuing, of instructions for parallel execution, 4) the communication of data values through memory via loads and stores, and 5) committing the process state in correct order so that precise interrupts can be supported. Examples of recent superscalar microprocessors, the MIPS RIOOOO, the DEC 21164, and the AMD K5 are used to illustrate a variety of superscalar methods.

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Section: B Instruction Decoding Renaming and Dispatchmentioning

confidence: 99%

The microarchitecture of superscalar processors

1995

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“…The branch predictor is very important to this scheme, since (unlike the piecewise data flow model of Requa and McGraw [10], for example) we allow out-of-order execution to take place across branch boundaries. Current Work and Concluding Remarks Our current research is taking HPS along four very different tracks, as we attempt to understand the limits of this microarchitecture.…”

Section: T H E H P S Model Of Executionmentioning

confidence: 99%

Aquarius

Despain

Patt

Srini

et al. 1987

SIGARCH Comput. Archit. News

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I n t r o d u c t i o n . O v e r v i e w .The Aquarius project [1] has, as the fundamental goal of its research, to establish the principles by which very large improvements in performance can be achieved in machines specialized for calculating difficult problems in design automation, expert systems, and signal processing. These problems are characterized by having substantial numeric and symbolic components. We are committed to the eventual design of a very high performance heterogeneous MIMD multiprocessor tailored to the execution of both numeric and logic calculations. Aquarius began in 1983. By 1985 we had completed and demonstrated the Aquarius I system [15] which was a small heterogeneous multiprocessor. Aquarius I achieved about an order of magnitude higher performance than had been achieved up to that time. For example, the Japanese Fifth Generation Computer 'PSI' had achieved 30 KLIPS in 1985. We are currently focusing on an experimental multiprocessor architecture (Aquarius II) for the high performance execution of Prolog that will contain 12 processors specialized for Prolog and others for a total of 16 processors. R e s e a r c h M e t h o d o l o g yIt is worth stating at the outset a number of key concepts which reflect our fundamental methodology for doing research in high performance knowledge processing systems. We believe in a research environment where systems evolve, taking advantage of contributions from a number of sources, both within and outside Berkeley.Second, we believe that issues should be dealt with as quickly and inexpensively as possible: by gadanken experiments, if possible, else analyzing, else simulation, else emulation and finally, only if required, by constructing and analyzing machines.Third, the nature of the high performance execution demands the effective utilization of enormous amounts of memory, coupled both loosely and tightly, it involves exploiting parallelism at both course and fine grain granularities, and it necessitates modularization of the system architecture to accommodate improvements in any element in the structure.Fourth, we are interested in proving concepts, rather than engineering manufactured parts. Thus, we are interested in building experimental architectures which can then be transferred to sites more appropriate than us for fabrication to achieve higher performance and more reliable systems. We are interested in using as many standard components and buses as possible in the experimental machine. This will facilitate the rapid transfer of the architecture technology.Fifth, we believe in working closely with government and industry.

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“…Section 2 describes the generic HPS (High Performance Substrate) [4,5,6] model of execution. Section 3 defines the architecture of HPSm, a minimal functionality variant of the HPS model.…”

Section: Outline Of This Reportmentioning

confidence: 99%

HPSm, a high performance restricted data flow architecture having minimal functionality

Hwu

Patt

1986

SIGARCH Comput. Archit. News

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Our recent work in microarchitecture has identified a new model of execution, restricted data flow, in which data flow techniques are used to coordinate out-of-order execution of sequential instruction streams. We believe that the restricted data flow model has great potential for implementing very high performance computing engines. This paper defines a minimal functionality variant of our model, which we are calling HPSm. The instruction set, data path, timing and control of HPSm are all described. A simulator for HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. We report the measurements obtained from these benchmarks, along with the measurements obtained for the Berkeley RISC II. The results are encouraging.

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Critical issues regarding HPS, a high performance microarchitecture

Cited by 17 publications

References 2 publications

The microarchitecture of superscalar processors

The microarchitecture of superscalar processors

Aquarius

HPSm, a high performance restricted data flow architecture having minimal functionality

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