Critical area and critical levels calculation in IC yield modeling

Gandemer, S.; Tremintin, Bernard; Charlot, J.-J.

doi:10.1109/16.2435

Cited by 63 publications

(9 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The average number of faults per module is therefore . In addition, when using the Poisson model, the faults in any distinct subareas are statistically independent, and thus (29) and the yield of the chip is (30) Although the Poisson distribution lends itself very easily to yield calculations, unfortunately it does not match actual defect and fault data. If any of the compound Poisson distributions is to be used, then the different modules on the chip are not statistically independent but rather correlated with respect to the number of faults.…”

Section: ) Chips With One Type Of Modulementioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

View full text Add to dashboard Cite

show abstract

Section: ) Chips With One Type Of Modulementioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

View full text Add to dashboard Cite

show abstract

“…The fault probability kernel, K(x-w), i.e., the probability that a defect of arbitrary size x will be fatal to a pattern of width w depends only on the pattern geometry. When the design layout is known, it can be obtained analytically [14], [15] or by simulation [16]- [18].…”

Section: Mature Yield Modelingmentioning

confidence: 99%

Forecast of CMOS Imagers Yield Learning by the Gompertz Model

Organtini¹,

Russo

2013

IEEE Trans. Semicond. Manufact.

View full text Add to dashboard Cite

This paper presents a novel approach to modeling yield using the Gompertz function, which is widely used in biology to model the growth processes of plants, tumors, etc. We demonstrate that the yield-learning process in a semiconductor fab follows the same behavior of the growth of biological systems. We start with a simple time series model, which describes the learning process in terms of defect density reduction. Then we obtain the Gompertz growth model, which also fits the experimental data better than more traditional learning models such as the Gruber's general yield learning model [38].

show abstract

“…with @)spot in (6) and (7), the lateral critical region for isolated-spot defects of a is established if (6) is satisfied, and it is found according to (7). Comer critical regions for isolated-spot defects can be derived from (9) if (8) is satisfied.…”

Section: Critical Regions For Isolated Spot Defectsmentioning

confidence: 99%

“…In the same year a simple geometrical method to extract critical areas from complex layouts was described [26]. Since then, the role of critical areas has been studied in greater detail [7]- [9], [14], [16], [40]. However, most of the analyses have considered very simple layouts, in particular, cases addressing only single-layer conductors and overlapped areas among layers.…”

mentioning

confidence: 99%

IC defect sensitivity for footprint-type spot defects

Gyvez

1992

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-While it is important to exhaustively verify IC designs for their functional performance, it is equally important to verify their robustness against spot defects, that is, to foresee what will happen to the design when it is exposed to defect conditions in a real manufacturing environment. One such verification is done by extracting the layout sites sensitive to defects. These sites are the places where defects can induce a functional failure of the design. Initial attempts to perform this verification task were based on a "critical area extraction" of one layer at a time. However, this extraction neglects the electrical significance of interrelationships between layers, as could be the case with transistors, vias, etc. In this paper we present a novel method to construct deterministically multilayer critical areas. These critical areas are established on the theoretical basis of defect semantics and on the new concept of "susceptible sites." Based on these foundations, we developed a system comprising several algorithms which in principle maintain simultaneously as many scan lines as the number of layers, in such a way that it is possible to keep track of the vertical and horizontal effects of defects. The paper also presents experimental timing results and a case study for diagnosing defect-fault information on an IC.

show abstract

Critical area and critical levels calculation in IC yield modeling

Cited by 63 publications

References 6 publications

Defect tolerance in VLSI circuits: techniques and yield analysis

Defect tolerance in VLSI circuits: techniques and yield analysis

Forecast of CMOS Imagers Yield Learning by the Gompertz Model

IC defect sensitivity for footprint-type spot defects

Contact Info

Product

Resources

About