CRISP: Cutting Edge Reconfigurable ICs for Stream Processing

Ahonen, Toni; Braak, Timon D. ter; Burgess, Stephen T.; Geißler, Richard; Heysters, P.M.; Hurskainen, Heikki; Kerkhoff, Hans G.; Kokkeler, André B.J.; Nurmi, Jari; Raasakka, Jussi; Rauwerda, G.K.; Smit, Gerard J. M.; Sunesen, Kim; Zonneveld, Henk van; Vermeulen, Bart; Zhang, Xiao

doi:10.1007/978-1-4614-0061-5_9

Cited by 20 publications

(10 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This coarse-grained reconfigurability of execution units is fast and done at run time. Instances of the tile-based multicore architecture template are demonstrated in Integrated Circuit (IC) [2,50] and Field-Programmable Gate Array (FPGA) [51].…”

Section: Kahrismamentioning

confidence: 99%

“…digital video processing, telecoms, and security applications) that need to process huge amounts of data in a short time would benefit from these attributes. Research projects such as MORPHEUS [1] and CRISP [2] have demonstrated the feasibility of such an approach and presented the benefit of parallel processing on real hardware prototypes. Providing a set of programming tools for respective cores is however not enough.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Compiling Scilab to high performance embedded multicore systems

Stripf¹,

Oey²,

Bruckschloegl³

et al. 2013

Microprocessors and Microsystems

Self Cite

View full text Add to dashboard Cite

Section: Kahrismamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compiling Scilab to high performance embedded multicore systems

Stripf¹,

Oey²,

Bruckschloegl³

et al. 2013

Microprocessors and Microsystems

Self Cite

View full text Add to dashboard Cite

“…While there are other efforts as well to produce parallel code for execution on embedded or other special type platofrms, like MORPHEUS [8], CRISP [9] and MEGHA [10], they usually are tailored to the target architecture. MORPHEUS and CRISP attempt to leverage reconfigurable logic, while MEGHA targets manycore GPU systems starting with MAT-LAB.…”

Section: Introductionmentioning

confidence: 99%

Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems

Goulas

Valouxis²,

Alefragis³

et al. 2013

2013 Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

International audienceAs processors and systems-on-chip increasingly become multicore, parallel programming remains a difficult, time-consuming and complicated task. End users who are not parallel programming experts have a need to exploit such processors and architectures, using state of the art fourth generation of high programming languages, like Scilab or MATLAB. The ALMA toolset addresses this problem by receiving Scilab code as input and produces parallel code for embedded multiprocessor systems on chip, using platform quasi-agnostic optimisations. In this paper, coarse grain parallelism extraction and optimization issues as well as parallel code generation for the ALMA toolset are discussed

show abstract

“…The DeSyRe baseline SoCs consist of multiple heterogeneous processing cores, such as Xentium DSP cores [7], on-chip memory blocks, RISC processors, and custom accelerator blocks interconnected by a Network-onChip (NoC). Fault-tolerance extensions to existing NoC approaches [8,9] as implemented in [10,11], respectively, are considered in DeSyRe. The heterogeneous baseline SoC is implemented in the fault-prone part of the DeSyRe system.…”

Section: Baseline Implementation Platformmentioning

confidence: 99%

DeSyRe: On-demand system reliability

Sourdis

Strydis²,

Armato³

et al. 2013

Microprocessors and Microsystems

View full text Add to dashboard Cite

a b s t r a c tThe DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect-/fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints.

show abstract

CRISP: Cutting Edge Reconfigurable ICs for Stream Processing

Cited by 20 publications

References 19 publications

Compiling Scilab to high performance embedded multicore systems

Compiling Scilab to high performance embedded multicore systems

Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems

DeSyRe: On-demand system reliability

Contact Info

Product

Resources

About