CPU and GPU Accelerated Fully Homomorphic Encryption

Abstract

Fully Homomorphic Encryption (FHE) is one of the most promising technologies for privacy protection as it allows an arbitrary number of function computations over encrypted data. However, the computational cost of these FHE systems limits their widespread applications. In this thesis, our objective is to improve the performance of FHE schemes by designing efficient parallel frameworks. In particular, we choose Torus Fully Homomorphic Encryption (TFHE) [1] as it offers exact results for an infinite number of boolean gate (e.g., AND, XOR) evaluations. We first extend the gate operations to algebraic circuits such as addition, multiplication, and their vector and matrix equivalents. Secondly, we consider the multi-core CPUs to improve the efficiency of both the gate and the arithmetic operations. Finally, we port the TFHE to the Graphics Processing Units (GPU) and device novel optimizations for boolean and arithmetic circuits employing the multitude of cores. We also experimentally analyze both the CPU and GPU parallel frameworks for different numeric representations (16 to 32-bit). Our GPU implementation outperforms the existing technique [1], and it achieves a speedup of 20× for any 32-bit boolean operation and 14.5× for multiplications.

MATCHA: A Fast and Energy-Efficient Accelerator for Fully Homomorphic Encryption over the Torus

“…In order to realize practical TFHE-based computing, it is critical to accelerate TFHE gates by specialized hardware. However, TFHE is only well-implemented on CPUs [16] and GPUs [7]. Although a recent work [10] accelerates TFHE gates on a FPGA, the TFHE gate latency on the FPGA is much longer than that on a GPU.…”

ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse

“…The maximum number of slots included in a single message m is determined by N as n ≤ N /2. We perform this transformation by computing the Inverse Discrete Fourier Transform (IDFT) of m, multiplying a scale factor ∆, (typically ranging from 2 40 to 2 60 ) and rounding the result: Ciphertext encrypting a message m.…”

“…However, the limited on-chip storage capacity of the GPU hinders kernel fusion for some functions [48]. Yet there are other GPU acceleration works [55], [60], [62], [78] targeting boolean HE schemes [22], [27]. FPGA/ASIC designs for HE: Prior works have implemented hardware logic for HE ops using FPGAs [49], [50], [70], [72] and ASICs [68], [74].…”

Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52

“…GPUs implementations of HE, (e.g. [14,17]) however, often restrict < 2 32 since 64-bit support for integers is often restricted or emulated, yielding lower performance. As such, the Intel HEXL API uses unsigned 64-bit integers input vector types.…”

“…Ciphertexts in many HE schemes are polynomials in finite fields, whose coefficients can be hundreds of bits and whose degree is typically a power in the range [2 10 , 2 17 ]. Performing HE computations requires operating on these large polynomials.…”