Coupled electro-thermal simulation of MOSFETs

Ni, Chunjian; Akšamija, Zlatan; Murthy, Jayathi Y.

doi:10.1007/s10825-012-0387-x

Cited by 22 publications

(12 citation statements)

References 31 publications

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“…Previously, it was reported that the peak temperature of the FDSOI devices is located close to the drain end of the device [1], [7] and the peak temperature value in FDSOI FETs is found to be much higher than the one in the conventional bulk MOSFETs [8]. The higher peak temperature of the FDSOI structure is mainly due to the thermal behaviour of its constitutive materials.…”

Section: Introductionmentioning

confidence: 93%

Thermal issues in deep sub-micron FDSOI circuits

Baltacı

Leblebici

2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Abstract-Self-heating effects became more prominent with the introduction of the modern devices like FDSOI and low thermal conductivity materials such as SiO2. Consequently, the design of high speed digital circuits which are the timecritical blocks of high performance processors started to be limited mainly by thermal issues. For observing the thermal behaviour of FDSOI structure on circuit level, a 64-bit KoggeStone parallel prefix adder is designed and implemented in 40nm bulk CMOS technology and thermal model of the circuit is extracted and simulated according to FDSOI design parameters. The implemented adder circuit has a critical path delay of 148ps under 900 mV power supply voltage with a power consumption of 12mW. The temperature profile of the designed circuit is extracted with thermal simulations and the peak temperature locations are examined in detail. The hot spot locations and their temperature values are correlated with the power density. It is shown that self-heating of high power density devices has a significant influence on the peak temperature of a design. Finally, a simple design solution is proposed which can significantly decrease the peak temperature.Keywords-High speed digital, FDSOI, self-heating, thermal simulations, reliability I. INTRODUCTIONThe demand for increasing the performance of high speed digital circuits brings the need for smaller and faster implementations [1]. However, as the clock frequencies increase owing to smaller technology nodes, the circuits consume power in higher densities. Consequently, the temperature levels are elevated and the thermal issues become the bottleneck of the circuits by altering the performance and decreasing the lifetime. On the performance side, the temperature induced reduced mobility decreases the device current and the maximum speed of operation [2]. Moreover, the threshold voltage decreases with the temperature and this results in higher leakage current and power consumption [3]. Higher power consumption brings higher temperature and this might result in thermal runaway where the die fails due to the uncontrolled increase in the temperature. In case thermal runaway does not happen, the chip might settle down to a higher temperature, which will degrade the performance as well as the reliability of the chip [4]. Electromigration phenomena is another reliability problem related to temperature where the metal interconnects are broken due to diffusion or flow of atoms under very high current densities at high temperatures [5]. All of the mentioned problems show that having a reliable and high performance chip is not possible without considering the thermal behaviour of the design. This brings another aspect into the design space, which is the self-heating.

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Section: Introductionmentioning

confidence: 93%

Thermal issues in deep sub-micron FDSOI circuits

Baltacı

Leblebici

2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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“…The consequence is having a longer conduction time. Since the PO and PI devices are ON for longer durations when compared to the other groups, they have higher average power density values according to (12) and they become the most critical devices in terms of creating a hotspot.…”

Section: Self-heating Of Devices With Different Functionsmentioning

confidence: 99%

“…Previously, it was reported that the peak temperature of the FDSOI devices is located close to the drain end of the device [1,10,11] and the peak temperature value in FDSOI FETs is found to be much higher than the one in the conventional bulk MOSFETs [12,13]. The higher peak temperature of the FDSOI structure is mainly due to the thermal behaviour of its constitutive materials.…”

Section: Introductionmentioning

confidence: 95%

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Baltacı

Leblebici

2017

Integration

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A B S T R A C TThermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40 nm node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations and hotspot locations are studied. The influence of local power density on peak temperature is examined. It is shown that high power density devices have significant influence on peak temperature in FDSOI. It is found that some group of devices that perform the same function are the most prominent heat generators. A modification on the design of these devices is proposed which decreases the hotspot temperatures significantly.

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“…15 Hatakeyama and Fushinobu 17 employed a similar model to study the thermal cross-talk between the nMOS and pMOS FETs of 90 nm channel length that were set side-by-side to design a CMOS gate. Although these approaches-strongly efficient in terms of computational resources-capture some aspects of the out equilibrium energy transfers that are involved in sub-micron devices, they are not suitable to provide a deep microscopic insight of phonon transport 18 19 They simulated a simple 1D n-i-n Si device. However, the contribution of optical phonons was neglected.…”

Section: Introductionmentioning

confidence: 99%

New insights into self-heating in double-gate transistors by solving Boltzmann transport equations

Nghiem

Saint-Martin

Dollfus

2014

Journal of Applied Physics

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On the origin of the mobility reduction in n-and p-metal-oxide-semiconductor field effect transistors with hafnium-based/metal gate stacks Schrödinger equation Monte Carlo in three dimensions for simulation of carrier transport in three-dimensional nanoscale metal oxide semiconductor field-effect transistors Electron mobility in double gate silicon on insulator transistors: Symmetric-gate versus asymmetric-gate configuration J.Electro-thermal effects become one of the most critical issues for continuing the downscaling of electron devices. To study this problem, a new efficient self-consistent electron-phonon transport model has been developed. Our model of phonon Boltzmann transport equation (pBTE) includes the decay of optical phonons into acoustic modes and a generation term given by electron-Monte Carlo simulation. The solution of pBTE uses an analytic phonon dispersion and the relaxation time approximation for acoustic and optical phonons. This coupled simulation is applied to investigate the self-heating effects in a 20 nm-long double gate MOSFET. The temperature profile per mode and the comparison between Fourier temperature and the effective temperature are discussed. Some significant differences occur mainly in the hot spot region. It is shown that under the influence of self-heating effects, the potential profile is modified and both the drain current and the electron ballisticity are reduced because of enhanced electron-phonon scattering rates. V C 2014 AIP Publishing LLC. [http://dx.

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Coupled electro-thermal simulation of MOSFETs

Cited by 22 publications

References 31 publications

Thermal issues in deep sub-micron FDSOI circuits

Thermal issues in deep sub-micron FDSOI circuits

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

New insights into self-heating in double-gate transistors by solving Boltzmann transport equations

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