Counter Based Low Power, Low Latency Wallace Tree Multiplier Using GDI Technique for On-chip Digital Filter Applications

Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters

“…This circuit has 106 transistors and consumes high power. By using the GDI technique a 5:3 counter was presented with multi‐input GDI AND, OR, and XOR gates [14]. Compared to the CMOS it has a smaller area therefore it is expected low power consumption.…”

“…For the physical structure and showing the accomplished novelty, Table 5 is provided, where the proposed 5:3 counter with 34 transistors and 14 gates, has the minimum area with at least 2x reduction regarding transistors' numbers compared to [12,14]. Also, for the proposed 7:3 counter this reduction is about 2.57x, 3.21x, 3.21x, 3.46x, and 4.64x compared to [18][19][20]-Design2, [4], and [20]-Design1, respectively.…”

“…Extracted results for 5:3 counters are provided in Table 3 while for 7:3 counters are summarised in Table 4. For 5:3 counters, the proposed one has the minimum results, 7.39 fJ as average power-delay-product (PDP), and in both evaluated points has 2.4x and 3.15x improvement compared to [12,14], respectively. Also, the nearest competitor to the proposed 5:3 counter is [15] with 1.262 e −22 J and 1.1056 e −22 J as energydelay products (EDPs) under two considered V DD values which show 72.77% and 50.55% worse results compared to proposed cell.…”