COTS-Based High-Performance Computing for Space Applications

Esposito, Stefano; Albanese, Cristian; Alderighi, M.; Casini, F.; Giganti, L.; Esposti, M. L.; Monteleone, Claudio; Violante, M.

doi:10.1109/tns.2015.2492824

Cited by 19 publications

(8 citation statements)

References 23 publications

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“…Both the National Agency for Space and Aviation (NASA) and the European Space Agency (ESA) expressed their interest in such systems, for example the ESA funded a set of research programs focused on COTS use for space applications [12].…”

Section: Previous Workmentioning

confidence: 99%

System-level architecture for mixed criticality applications on MPSoC: A space application

Esposito

Violante

2017

2017 IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace)

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This paper discusses SEE effects in an architecture based on commercial-off-the-shelf multicore processors for consolidating mixed criticalities applications in single board computers for space applications. This paper builds on previously proposed system-level architectures for mixed-criticality applications, describing them both for convenience together with the previous validation results. The paper proposes a case study on a real space application. Based on reliability and availability requirements of a European Space Agency mission, the paper shows how the proposed solutions can meet availability requirements in two different radiation environments.

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Section: Previous Workmentioning

confidence: 99%

System-level architecture for mixed criticality applications on MPSoC: A space application

Esposito

Violante

2017

2017 IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace)

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“…The main advantages of COTS hardware over custom-made, in-house, or commissioned counterparts are substantial cost savings, reduced development time, improved performance, and current technology node. In the areas previously dominated by customised hardware components, COTS-based systems are gaining acceptance and applications [Engel, 2001;Esposito et al, 2015;Gansler and Lucyshyn, 2008;Hiergeist and Holzapfel, 2016]. Nevertheless, COTS hardware faults can have direct impacts on system reliability.…”

Section: Motivationmentioning

confidence: 99%

Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware

Shen

Elphinstone

2015

2015 11th European Dependable Computing Conference (EDCC)

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The thesis presents microkernel-based software-implemented mechanisms for improving the trustworthiness of computer systems based on commercial off-the-shelf (COTS) hardware that can malfunction when the hardware is impacted by transient hardware faults. The hardware anomalies, if undetected, can cause data corruptions, system crashes, and security vulnerabilities, significantly undermining system dependability. Specifically, we adopt the single event upset (SEU) fault model and address transient CPU or memory faults.We take advantage of the functional correctness and isolation guarantee provided by the formally verified seL4 microkernel and hardware redundancy provided by multicore processors, design the redundant co-execution (RCoE) architecture that replicates a whole software system (including the microkernel) onto different CPU cores, and implement two variants, loosely-coupled redundant co-execution (LC-RCoE) and closely-coupled redundant co-execution (CC-RCoE), for the ARM and x86 architectures. RCoE treats each replica of the software system as a state machine and ensures that the replicas start from the same initial state, observe consistent inputs, perform equivalent state transitions, and thus produce consistent outputs during error-free executions. Compared with other software-based error detection approaches, the distinguishing feature of RCoE is that the microkernel and device drivers are also included in redundant coexecution, significantly extending the sphere of replication (SoR).Based on RCoE, we introduce two kernel mechanisms, fingerprint validation and kernel barrier timeout, detecting fault-induced execution divergences between the replicated systems, with the flexibility of tuning the error detection latency and coverage. The kernel error-masking mechanisms built on RCoE enable downgrading from triple modular redundancy (TMR) to dual modular redundancy (DMR) without service interruption. We run synthetic benchmarks and system benchmarks to evaluate the performance overhead of the approach, observe that the overhead varies based on the characteristics of workloads and the variants (LC-RCoE or CC-RCoE), and conclude that the approach is applicable for real-world applications. The effectiveness of the error detection mechanisms is assessed by conducting fault injection campaigns on real hardware, and the results demonstrate compelling improvement.Declaration relating to disposition of project thesis/dissertation I hereby grant to the University of New South Wales or its agents the right to archive and to make available my thesis or dissertation in whole or in part in the University libraries in all forms of media, now or here after known, subject to the provisions of the Copyright Act 1968. I retain all property rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.I also authorise University Microfilms to use the 350 word abstract of my thesis in Dissertation Abstracts International (this is applica...

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“…In fact, COTS microprocessors are playing an important role in the New Space era, in which a growing number of actors apart from Space Agencies and Governments are involved. Increased efforts are being taken to study commercial parts to test and improve, if possible, their reliability [1][2].…”

Section: Introductionmentioning

confidence: 99%

Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS

Avilés

Lindoso

Belloch

et al. 2022

IEEE Trans. Nucl. Sci.

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Nowadays, high performance microprocessors are demanded in many fields, including those with high reliability requirements. Commercial microprocessors present a good tradeoff between cost, size and performance, albeit they must be adapted to satisfy the reliability requirements when they are used in harsh environments. This work presents a high-end multiprocessor hardened with a macro synchronized lockstep and additional protections. A commercial dual core ARM cortex A9 has been used as case study and a complete hardened system has been developed. Evaluation of the proposed hardened system has been accomplished with exhaustive fault injection campaigns and proton irradiation. The hardening approach has been accomplished for both baremetal applications and OS-based. The hardened system has demonstrated high reliability in all performed experiments with error coverage up to 99.3% in the irradiation experiments. Experimental irradiation results demonstrate a cross-section reduction of two orders of magnitude.

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COTS-Based High-Performance Computing for Space Applications

Cited by 19 publications

References 23 publications

System-level architecture for mixed criticality applications on MPSoC: A space application

System-level architecture for mixed criticality applications on MPSoC: A space application

Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware

Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS

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