Cost evaluation from specifications for BSP programs

Niculescu, Virginia

doi:10.1109/ipdps.2006.1639626

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…Its level structure contains computing phase, whole communication phase and barrier synchronisation phase, vertical structure is consisted by supersteps [13]. A BSP computer can be defined by p processors, each with its local memory, connected via some means of point-to-point communication.…”

Section: Bspmentioning

confidence: 99%

The Research of Synthesizing Parallel Computing Models with Graph Reduction

Shen¹,

Tong²

2014

IJAST

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Section: Bspmentioning

confidence: 99%

The Research of Synthesizing Parallel Computing Models with Graph Reduction

Shen¹,

Tong²

2014

IJAST

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“…This programming paradigm uses custom built data redistribution libraries, making large scale codes easier to write and maintain [2]- [4]. At the same time, this programming model allows for the analysis of application performance using the Bulk Synchronous Parallel (BSP) machine model introduced by Valiant [5], or the Decomposable BSP (DBSP) machine extension that models submachine locality [6], [7].…”

Section: A Cost Modelmentioning

confidence: 99%

“…For example, inter-core bandwidth is higher than intra-socket bandwidth, which is higher than the networking chip bandwidth. Moreover, large scale machines are not able to provide full bisection width bandwidth 6 at the top of their router hierarchy 7 . This unbalance becomes more prevalent as more cores are packed into a box, and system designers are forced to make a tradeoff between the number of cores, percore bandwidth, and switch size.…”

Section: B System Designmentioning

confidence: 99%

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Estimating Application Hierarchical Bandwidth Requirements Using BSP Family Models

Soviani

Singh

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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There has been a vast amount of work to develop programming models that provide good performance across machine architectures, are easy to use, and have predictable performance. Similarly, the design and optimization of architectures to achieve optimal performance for an application class remains a challenging task. Accurate cost modeling is essential for both application development and system design.Many scientific computing codes are developed by using libraries that provide custom-built collective communication primitives. For example, the family of Bulk Synchronous Parallel (BSP) machine models provides suitable tools for analyzing such problems. However, modeling the effect of bandwidth limitations for globally unbalanced communication and estimating the hierarchical bandwidth used by applications remain key challenges.We present a hierarchical bandwidth machine model (alphaDBSP) that naturally extends the Decomposable BSP (DBSP) model by associating a bandwidth growth factor alpha to each message pattern. Algorithms executed on alphaDBSP have a runtime that is at least as good as DBSP. Hence, there are globally unbalanced problems for which alphaDBSP analysis is simpler or more accurate 1 . We present three scientific computing kernels that illustrate the differences between alphaDBSP and DBSP analysis.Similar to the BSP family models, alphaDBSP predicts collective communication execution time for a given machine. Additionally, alphaDBSP estimates the hierarchical bandwidth required by a given application. System architects may use this estimation to design machines that avoid bandwidth bottlenecks for their target application class.

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