Cost effective solution using inverse lithography OPC for DRAM random contact layer

Jun, Jinhyuck; Hwang, Jaehee; Choi, Jae-Seung; Oh, Se‐Young; Park, Chanha; Yang, Hyunjo; Dam, Thuc; Do, Munhoe; Lee, Jun Young; Xiao, Gao; Choi, Jung-Hoe; Lucas, Kevin

doi:10.1117/12.2257857

Cited by 2 publications

(1 citation statement)

References 2 publications

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“…Advanced memory designs require advanced lithographic techniques to print desired features. As lithographic pitches approach the resolution limit for 193nm lithographic systems, techniques like double patterning and computational lithographic are needed to meet the design specifications [1]. High-cost double exposure and double etch processes to meet lithographic requirements have promoted the use of computation resolution enhancement technologies (RETs) like inverse lithography [2]- [3].…”

Section: Introductionmentioning

confidence: 99%

Full chip inverse lithography technology mask synthesis for advanced memory manufacturing

Digaum¹,

Chiang

Wang

et al. 2023

DTCO and Computational Patterning II

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In advanced semiconductor memory manufacturing, the feature size keeps aggressively shrinking, creating problems in the fabrication process and leading to decreasing yield. Three key factors that can impact memory process and yield are lithographic process window, full field CD uniformity (CDU), and correction run time performance. In this paper, we describe and present a mask processing technique utilizing a) global array detect (GAD) for detecting and optimizing cell repetition, b) periodic boundary condition (PBC) for preserving simulation and mask symmetry, and c) cell-level ILT (CLILT) flow to process repeated cell regions and blend various design parts. With GAD + PBC + CL-ILT processing, we can achieve a perfectly consistent mask array region with enlarged process window and minimum local CD variation for a full field mask. Moreover, with fewer pattern units (called templates) to process, we can complete full chip ILT with reasonable time and compute resources compared to OPC full chip correction. In this paper, we show simulation and wafer print results including pattern fidelity, process window, mask consistency, and run time data.

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Section: Introductionmentioning

confidence: 99%