Cost and cycle time performance of fabs based on integrated single-wafer processing

Abstract

Visions of future wafer fabs include the use of integrated single-wafer processors to achieve fast cycle times and contain rising production costs. A survey of IC manufacturers, equipment vendors, and IC manufacturing literature was used to generate hypothetical conventional and alternative fabs to evaluate the effect of integrated single-wafer processing on cycle time and cost performance. The distinguishing features of the alternative fab are 1) all thermal processes performed on singlewafer processors; 2) back-end wet cleans performed on singlewafer processors; 3) integration of single-wafer processors into clusters or cells wherever practical, and 4) extensive use of insitu insitu insitu process monitors to replace in-line process monitors. Modeling and simulation of the resulting fabs suggest that integrated singlewafer processing can reduce the cycle time of conventional fabs by about 50% without having a significant effect on wafer production cost. Tool integration and single-wafer processing must be used together to achieve these performance improvements. Although traditional lot sizes appeared to be appropriate for both fabs, improvements in cluster tool reliability and process step similarity could change optimal integrated tool configurations and reduce optimal lot sizes in the future.

Forecasting the Unit Cost of a Product with Some Linear Fuzzy Collaborative Forecasting Models

“…Carnes also compared the long-term costs of ownership of two alternative machines, but these costs were not allocated to the two machines. Wood [16] defined the lowest cost of all operations on the same machine as the minimum wafer cost. In Pfitzner et al's view, the recovery of wafers is becoming increasingly important in reducing the unit cost along with the growth in size of a wafer [17].…”

A hybrid approach for modelling and analysis of an integrated machine

“…In the processbound region, changes in process times and transport times would affect the throughput of the cluster tool. There are some cases where a lot size reduction can decrease the maximum tool throughput [13]. Some process tools require set-ups or other overhead times that are independent of the lot size.…”

An Improved Fuzzy Collaborative System for Predicting the Unit Cost of a DRAM Product

“…In the literature, Carnes has established the equation for calculating the unit cost of a wafer. Wood estimated the smallest increment in the unit cost of a wafer because of the use of a processing tool. Dong and Xie proposed two models, the wafer/die cost model and bonding cost model, to estimate the unit cost of a three‐dimensional integrated circuit.…”