Correlation between deep depletion and current–voltage saturation of SrTiO3 gate dielectric capacitor

Liu, C. Y.; Tseng, Tseung‐Yuen

doi:10.1016/j.ceramint.2003.12.020

Cited by 14 publications

(5 citation statements)

References 8 publications

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“…The peak value of capacitance is found to vary with series resistance, inter- face-state density, and frequency of the ac signal [32,33]. The series resistance is an important parameter, which causes the electrical characteristics of MS and MIS-Schottky diodes to be non-ideal [12][13][14][15][16][17].…”

Section: Forward and Reverse Bias C-v And G/x-v Characteristicsmentioning

confidence: 99%

“…The interface quality between the deposited metal and the semiconductor surface decides the performance and reliability of these devices. Therefore, in order to reduce the leakage current and interface-state density, a variety of gate oxides/insulators such as Al 2 O 3 [3,6,7], ZrO 2 [9], SiN x [4,5,10], SrTiO 3 [12], Bi 3 Ti 4 O 12 [14], HfO 2 [15], and SiO x N y [16] materials have been proposed for application as an insulator layer at the metal/semiconductor (M/S) interface in semiconductor devices such as a metal-insulator-semiconductor (MIS) or metal-oxide-semiconductor (MOS), metal-ferroelectric-semiconductor (MFS) or metal-ferroelectric-insulator-semiconductor (MFIS), metaloxide-semiconductor field effect transistor (MOSFET), MFISFET structures and high-electron-mobility-transistors (HEMTs) [3][4][5][6][7][8][9][10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

“…Various passivation materials have been reported to control surface states and decrease a leakage current of AlGaN/GaN HEMTs [6,7]. The fundamental requirements for the materials are high dielectric constant [3][4][5][6][7][8][9][10][11][12][13][14][15][16]. The interface quality between the deposited metal and the semiconductor surface decides the performance and reliability of these devices.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Electrical characterization of MS and MIS structures on AlGaN/AlN/GaN heterostructures

Arslan

Bütün

Şafak

et al. 2011

Microelectronics Reliability

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The forward and reverse bias I-V, C-V, and G/ω-V characteristics of (Ni/Au) Schottky barrier diodes (SBDs) on the Al 0.22Ga 0.78N/AlN/GaN high-electron-mobility-transistor (HEMTs) without and with SiN x insulator layer were measured at room temperature in order to investigate the effects of the insulator layer (SiN x) on the main electrical parameters such as the ideality factor (n), zero-bias barrier height ( B0), series resistance (R s), interface-state density (N ss). The energy density distribution profiles of the N ss were obtained from the forward bias I-V characteristics by taking into account the voltage dependence of the effective barrier height ( e) and ideality factor (n V) of devices. In addition, the N ss as a function of E c-E ss was determined from the low-high frequency capacitance methods. It was found that the values of N ss and R s in SBD HEMTs decreases with increasing insulator layer thickness. © 2010 Elsevier Ltd. All rights reserved

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Section: Forward and Reverse Bias C-v And G/x-v Characteristicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Electrical characterization of MS and MIS structures on AlGaN/AlN/GaN heterostructures

Arslan

Bütün

Şafak

et al. 2011

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…However, the capacitance of sample MOS-C was larger than that of sample MOS-A; and the capacitance of sample MOS-D was larger than that of sample MOS-C. The Si grains of the sample MOS-C recrystallized during the high temperature process, thus reducing the amount of bulk traps within the implanted layer [16]. The larger capacitance of sample MOS-D than MOS-C indicated that the RTA process resulted in more traps retained within the implanted layer.…”

Section: Resultsmentioning

confidence: 87%

Rapid Thermal Treatment for Improving Thermal Processing Stability of Ar-Implanted Surface Passivated High-Resistivity Silicon

Liu

Weng

Lin

2011

IEEE Microw. Wireless Compon. Lett.

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This study improved the thermal processing stability of Si-based coplanar waveguides (CPW) through Ar ion implantation with rapid thermal annealing (RTA). Ar ion implantation damaged the surface layer of the high-resistivity silicon substrate, which decreased attenuation of the CPW line. However, the damaged layer recrystallized during a high temperature process, which caused thermal processing instability. A RTA process was performed to retard the epitaxial regrowth from the substrate, this improved thermal processing stability and decreased dc-voltage dependence of the attenuation of the CPW line. These improved properties were found to be due to the RTA process retaining more bulk traps within the damaged layer.Index Terms-Coplanar waveguide (CPW), microwave loss, surface passivation, thermal processing stability, thermally-induced electrical instability.

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“…18 Without the minority carriers from the source and drain of the metal-oxide-semiconductor fieldeffect transistor, the minority carriers of the inverted p-MOSCAP are insufficient, especially for the device with an ultra-thin oxide layer. 26,27 The number of inversion electrons in the device edge region (Q n ) in our experiment is thus limited for the electron leakage through ultrathin oxide. A small value of the Q n results in the small V OX,E and large ϕ E , and further contributes to the small inversion dark current.…”

Section: Resultsmentioning

confidence: 99%

Sensitivity Enhancement of Metal-Oxide-Semiconductor Tunneling Photodiode with Trapped Electrons in Ultra-Thin SiO₂Layer

Chen

Hwu

2014

ECS J. Solid State Sci. Technol.

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The enhancement of the photo sensitivity of Si-based metal-oxide-semiconductor (MOS) tunneling photodiode with an ultra-thin SiO2 layer is demonstrated by a simple bias treatment in this work. It was found that, after applying a negative constant voltage stress (NCVS) treatment onto the device, a few electrons would be trapped in the ultra-thin SiO2 layer, subsequently the trapped electrons led to a large decrement in the inversion dark current at positive bias. As a result, the photo sensitivity of the device at positive voltage was enhanced. Different stressing voltages of the NCVS treatments applied onto the device were utilized to achieve different numbers of trapped electrons. Thus different photo sensitivities of the device were obtained by these different treatments. The device with the trapped electrons of −0.29 pC exhibits a maximum photo sensitivity enhanced factor (31.3 at 1 V) in this experiment.

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Correlation between deep depletion and current–voltage saturation of SrTiO3 gate dielectric capacitor

Cited by 14 publications

References 8 publications

Electrical characterization of MS and MIS structures on AlGaN/AlN/GaN heterostructures

Electrical characterization of MS and MIS structures on AlGaN/AlN/GaN heterostructures

Rapid Thermal Treatment for Improving Thermal Processing Stability of Ar-Implanted Surface Passivated High-Resistivity Silicon

Sensitivity Enhancement of Metal-Oxide-Semiconductor Tunneling Photodiode with Trapped Electrons in Ultra-Thin SiO₂Layer

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Correlation between deep depletion and current–voltage saturation of SrTiO3 gate dielectric capacitor

Cited by 14 publications

References 8 publications

Electrical characterization of MS and MIS structures on AlGaN/AlN/GaN heterostructures

Electrical characterization of MS and MIS structures on AlGaN/AlN/GaN heterostructures

Rapid Thermal Treatment for Improving Thermal Processing Stability of Ar-Implanted Surface Passivated High-Resistivity Silicon

Sensitivity Enhancement of Metal-Oxide-Semiconductor Tunneling Photodiode with Trapped Electrons in Ultra-Thin SiO2Layer

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Product

Resources

About

Sensitivity Enhancement of Metal-Oxide-Semiconductor Tunneling Photodiode with Trapped Electrons in Ultra-Thin SiO₂Layer