Correct hardware synthesis

Perna, Juan Ignacio; Woodcock, Jim; Sampaio, Augusto; Iyoda, Juliano

doi:10.1007/s00236-011-0142-y

Cited by 3 publications

(2 citation statements)

References 21 publications

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“…This synthesis back end can seamlessly integrate with the proof-producing HOL4 to Verilog translator as it is based on the same Verilog semantics, and therefore creates verified translation from HOL4 circuit descriptions to synthesised Verilog netlists. Perna et al designed a formally verified translator from a deep embedding of Handel-C [Aubury et al 1996] into a deep embedding of a circuit [Perna and Woodcock 2012;Perna et al 2011]. Finally, Ellis [2008] used Isabelle to implement and reason about intermediate languages for software/hardware compilation, where parts could be implemented in hardware and the correctness could still be shown.…”

Section: Usable Toolmentioning

confidence: 99%

Formal verification of high-level synthesis

Herklotz

Pollard

Ramanathan

et al. 2021

Proc. ACM Program. Lang.

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High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.

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Section: Usable Toolmentioning

confidence: 99%

Formal verification of high-level synthesis

Herklotz

Pollard

Ramanathan

et al. 2021

Proc. ACM Program. Lang.

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“…In its original presentation, it describes nondeterministic sequential programming, the renement calculus, the algebra of programming, compilation of high-level languages, concurrency, communication, reactive processes, and higher-order programming [25]. Subsequently, it has been exploited in a diversity of areas such as component-based systems [49], hardware verication [40,39], and hardware/software co-design [2].…”

Section: Unifying Theories Of Programmingmentioning

confidence: 99%

Contracts in CML

Woodcock

Cavalcanti

Fitzgerald

et al. 2014

Lecture Notes in Computer Science

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We describe the COMPASS Modelling Language (CML), which is used to model large-scale Systems of Systems and the contracts that bind them together. The language can be used to document the interfaces to constituent systems using formal, precise, and veriable specications including preconditions, postconditions, and invariants. The semantics of CML directly supports the use of these contracts for all language constructs, including the use of communication channels, parallel processes, and processes that run forever. Every process construct in CML has an associated contract, allowing clients and suppliers to check that the implementations of constituent systems conform to their interface specications.

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Laws of Timed State Machines

Cavalcanti,

Conserva Filho,

Ribeiro

et al. 2023

The Computer Journal

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State machines are widely used in industry and academia to capture behavioural models of control. They are included in popular notations, such as UML and its variants, and used (sometimes informally) to describe computational artefacts. In this paper, we present laws for state machines that we prove sound with respect to a process algebraic semantics for refinement, and complete, in that they are sufficient to reduce an arbitrary model to a normal form that isolates basic (action and control) elements. We consider two variants of UML-like state machines, both enriched with facilities to deal with time budgets, timeouts and deadlines over triggers and actions. In the first variant, machines are self-contained components, declaring all the variables, events and operations that they require or define. In contrast, in the second variant, machines are open, like in UML for instance. Laws for open state machines do not depend on a specific context of variables, events and operations, and normalization uses a novel operator for open-machine (de)composition. Our laws can be used in behaviour-preservation transformation techniques. Their applications are automated by a model-transformation engine.

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Correct hardware synthesis

Cited by 3 publications

References 21 publications

Formal verification of high-level synthesis

Formal verification of high-level synthesis

Contracts in CML

Laws of Timed State Machines

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