Cores, Cache, Content, and Characterization: IBM’s Second Generation 14-nm Product, z15

Wolpert, David; Berry, Christopher J.; Bell, Brian; Jatkowski, Adam; Surprise, Jesse; Isakson, John; Geva, Ofer; Deskin, Brian; Cichanowski, Mark; Hamid, Dina; Cavitt, Chris; Fredeman, Gregory; Kannambadi, Dinesh; Saporito, Anthony; Mishra, Ashutosh; Buyuktosunoglu, Alper; Webel, Tobias; Lobo, Preetham; Bertran, Ramon; Parashurama, Pradeep Bhadravati; Chidambarrao, D.; Bruen, Brandon; Wagstaff, Alan; Lukes, Eric; Carey, Seán; Shi, Hunter; Romain, M; Logsdon, Paul; Agarwal, Ishita

doi:10.1109/jssc.2020.3030062

Cited by 6 publications

(4 citation statements)

References 12 publications

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“…Furthermore, offplatform GPU, ASIC or FPGA solutions have other disadvantages such as low-level programming requirements, proprietary drivers, lack of big-endian support, certification costs and limited RAS (Reliability, Availability and Serviceability) support. For example, in the case of RAS, chip target lifetime of GPU and ASIC solutions in the marketplace is far from 100,000 power-on hours that IBM Z processor chip supports [101]. On-platform PCIe attached GPU, ASIC, or FPGA solutions also have similar disadvantages as listed above.…”

Section: Integrated Ai Accelerator Design Decisionsmentioning

confidence: 99%

“…IBM Telum is the next generation chip for IBM z16 and LinuxONE systems [37] addressing the needs of enterprise class workloads. It provides improved performance, and system capacity in comparison to the predecessor z15 [9,72,101]. Figure 1 shows a die photo of the Telum chip.…”

Section: Introductionmentioning

confidence: 99%

“…IBM z15 [9,72,101] and prior system generations [10,11,17,28,50,51,80,95,96] implemented shared physical L3 caches on the processor chip, and had a separate chip that implemented a large L4 cache. The Telum design implements all of that logic in a single chip, and opts to quadruple the L2 cache to 32 MB with very low latency.…”

Section: Introductionmentioning

confidence: 99%

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AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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IBM Telum is the next generation processor chip for IBM Z and LinuxONE systems. The Telum design is focused on enterprise class workloads and it achieves over 40% per socket performance growth compared to IBM z15. The IBM Telum is the first server-class chip with a dedicated on-chip AI accelerator that enables clients to gain real time insights from their data as it is getting processed.Seamlessly infusing AI in all enterprise workloads is highly desirable to get real business insight on every transaction as well as to improve IT operation, security, and data privacy. While it would undeniably provide significant additional value, its application in practice is often accompanied by hurdles from low throughput if run on-platform to security concerns and inconsistent latency if run off-platform. The IBM Telum chip introduces an on-chip AI accelerator that provides consistent low latency and high throughput (over 200 TFLOPS in 32 chip system) inference capacity usable by all threads. The accelerator is memory coherent and directly connected to the fabric like any other general-purpose core to support low latency inference while meeting the system's transaction rate. A scalable architecture providing transparent access to AI accelerator functions via a non-privileged general-purpose core * This paper is part of the Industry Track of ISCA 2022's program.

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Section: Integrated Ai Accelerator Design Decisionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

Self Cite

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show abstract

“…As electronic clock generators are unable to drive the clock load directly, many levels of clock drivers have been employed to overcome the bandwidth limitations. Due to the large number of clock drivers in processors and digital systems, substantial power consumption occurs, accounting for 10–30% of overall chip power consumption 6 – 9 and causing on-chip thermal problems. As each clock driver adds timing uncertainty, jitter (random variation in clock arrival time) and skew (spatial variation in clock arrival time) performances are also significantly impaired.…”

Section: Introductionmentioning

confidence: 99%

Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses

Hyun

Chung

et al. 2023

Nat Commun

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A clock distribution network (CDN) is a ubiquitous on-chip element that provides synchronized clock signals to all different circuit blocks in the chip. To maximize the chip performance, today’s CDN demands lower jitter, skew, and heat dissipation. Conventionally, on-chip clock signals have been distributed in the electric voltage domain, resulting in increased jitter, skew, and heat dissipation due to clock drivers. While low-jitter optical pulses have been locally injected in the chip, research on effective distribution of such high-quality clock signals has been relatively sparse. Here, we demonstrate femtosecond-precision distribution of electronic clocks using driver-less CDNs injected by photocurrent pulses extracted from an optical frequency comb source. Femtosecond-level on-chip jitter and skew can be achieved for gigahertz-rate clocking of CMOS chips by combining ultralow comb-jitter, multiple driver-less metal-meshes, and active skew control. This work shows the potential of optical frequency combs for distributing high-quality clock signals inside high-performance integrated circuits, including 3D integrated circuits.

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