CORDIC implementation of digital heterodyne filter in VLSI

Kadam, S.; Soderstrand, M.A.; Johnson, L.G.

doi:10.1109/acssc.2001.986980

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B Architectural Optimization Of Cordic Based Nd Fica1

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2011

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Cited by 2 publications

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“…Considering 3D architecture (Fig. 3) first, since each of its three stages has two levels with different set of θ i , it is essential to use one (1 : 2) de-multiplexer and one (2 : 1) multiplexer at the θ i -outputs and Interested readers may look into [20]- [23] to get an insight of the implementation of CORDIC in silicon/FPGA and also into [24]- [28] to get an idea of quantization error and numerical accuracy of CORDIC.…”

Section: B Architectural Optimization Of Cordic Based Nd Ficamentioning

confidence: 99%

Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture

Acharyya

Maharatna

Al-Hashimi

et al. 2011

IEEE Trans. Signal Process.

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This paper proposes a low complexity n-dimensional (nD) FastICA algorithm and architecture by introducing the concept of co-ordinate rotation where n ≥ 2. The proposed algorithm can merge the two key steps of Conventional FastICA -Preprocessing and Update and is therefore capable of reducing the hardware complexity of the conventional FastICA significantly as demonstrated in this paper. Hardware implementation can further be simplified due to the recursive nature of the proposed algorithm where the same 2D hardware module can be used as the fundamental core to implement nD architecture. Together with the algorithm formulation, its functionality is also validated and hardware complexity is analyzed and compared with the conventional nD FastICA.

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