CORDIC-based FFT real-time processing design and FPGA implementation

Tang, Aimei; Yu, Li; Han, Fangjian; Zhang, Zhiqiang

doi:10.1109/cspa.2016.7515837

Cited by 13 publications

(8 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…However, they do not present results of circuit area and power dissipation that can support such statement. The work in [27] discusses the realization of a radix-2 FFT processor based on the CORDIC algorithm on FPGA. However, power results are not available.…”

Section: Related Workmentioning

confidence: 99%

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

Sapper

Paim

Costa

et al. 2021

JICS

View full text Add to dashboard Cite

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

show abstract

Section: Related Workmentioning

confidence: 99%

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

Sapper

Paim

Costa

et al. 2021

JICS

View full text Add to dashboard Cite

show abstract

“…Even more, the DFT algorithm can be exploited to perform a convolution operation, which is very helpful for major signal processing tasks. Indeed, there is a considerable interest in embedded systems to develop a new DFT processor which must be consistent and compliant with this paradigm: optimal metric performance in terms of latency, throughput, occupied area, and power consumption [7]. In addition, it has to provide adequate architectures, fast encoding algorithms, reliable and efficient communications protocol, an attractive quality of service along with the adaptive flow control and congestion [8].…”

Section: Literature Reviewmentioning

confidence: 99%

DFT processor implementation scheme based on Rader algorithm

Samiha

Benouaret

Harize

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

The implementation of a discrete Fourier transform (DFT) algorithm plays a key role in many real-time applications. This study mainly deals with the design and implementation of a DFT processor with non-power-of-two (prime) problem sizes using the Rader algorithm. The proposed design focuses on increasing the speed to fulfil the requirements of the real-time data transmission by enabling data rates up to 10 Gbps. Despite its limitation to the prime size, it remains a promising tool in the signal processing aspect and takes its place among other techniques to achieve high-speed wireless communication. By avoiding the cumbersome process during twiddle factors computation as well as the butterfly structure, the outcome preludes to an ambitious architecture dedicated to high-speed design reaching over 233 and 92 MHz for DFT lengths of 7 and 67, respectively, on Virtex 6. Thereby, the obtained results prove the efficiency of the algorithm and show the trade-off to be established in terms of occupied area, throughput, latency, and power consumption.

show abstract

“…where In the FPGA, the non-linear trigonometric functions required by the fuzzy module, generated from the module COordinate Rotation DIgital Computer (CORDIC) iterative [17], are implemented. The CORDIC algorithm is a method aimed at systems that do not have dedicated hardware arithmetic operations.…”

Section: Loss-of-field Protection Fuzzy (Loepf)mentioning

confidence: 99%

New Algorithm With Fuzzy Inference in Fpga to Field Loss Protection for Wind Turbine

Araújo¹,

Trondoli²

2016

International Journal of Power and Energy Systems

View full text Add to dashboard Cite

The present study aims to present the contribution of a new algorithm for synchronous generators wind protection and the assessment of the effectiveness of the performance of the Loss of Field Protection Fuzzy (LOEPF), using fuzzy inference implemented in reconfigurable computing with high-level optimization of logical operations. A new model of sub-and overexcitation by the wind generator capacity curve for the steady-state stability limit is introduced, serving as the basis for the development of this new algorithm and the evaluation of the effectiveness of the same. The LOEPF algorithm is implemented in Field Programmable Gate Array (FPGA) with acquisition of voltage and current signals, for carrying out the tests of various conditions of simulated faults by means of a test box Doble F6150 compared with the results obtained with the use of a commercial relay. The results obtained in tests of the new algorithm showed superior performance compared to conventional protection, reducing lag time and time of trip. This feature allows for fast data throughput and processing allowing the relay handling samples high-frequency data and computational efficiency.

show abstract

CORDIC-based FFT real-time processing design and FPGA implementation

Cited by 13 publications

References 7 publications

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

DFT processor implementation scheme based on Rader algorithm

New Algorithm With Fuzzy Inference in Fpga to Field Loss Protection for Wind Turbine

Contact Info

Product

Resources

About