CORDIC-Based Architecture for Computing Nth Root and Its Implementation

Luo, Yuanyong; Wang, Yuxuan; Sun, Huaqing; Zha, Yi; Wang, Zhongfeng; Pan, Hongbing

doi:10.1109/tcsi.2018.2835822

Cited by 30 publications

(22 citation statements)

References 28 publications

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“…The CORDIC is used to carry out a wide variety of applications from eigenvalue decomposition 19 – 21 to many real-time DSP applications 22 – 24 . In research 25 , the CORDIC-based efficient way to calculate the roots and powers is demonstrated which is based on logarithm and exponential. Operations like logarithm and exponential can be efficiently carried out by the CORDIC algorithm.…”

Section: Introductionmentioning

confidence: 99%

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Changela,

Kumar,

Woźniak

et al. 2023

Sci Rep

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In this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power computations are divided into three phases, and each phase is performed by a different class of the proposed modified radix-4 CORDIC algorithms in the proposed architecture. Although radix-4 CORDIC can converge faster with fewer recurrences, it demands more hardware resources and computational steps due to its intricate angle selection logic and variable scale factor. We have employed the modified radix-4 hyperbolic vectoring (R4HV) CORDIC to compute logarithms, radix-4 linear vectoring (R4LV) to perform division, and the modified scaling-free radix-4 hyperbolic rotation (R4HR) CORDIC to compute exponential. The criteria to select the amount of rotation in R4HV CORDIC is complicated and depends on the coordinates $$X^j$$ X j and $$Y^j$$ Y j of the rotating vector. In the proposed modified R4HV CORDIC, we have derived the simple selection criteria based on the fact that the inputs to R4HV CORDIC are related. The proposed criteria only depend on the coordinate $$Y^j$$ Y j that reduces the hardware complexity of the R4HV CORDIC. The R4HR CORDIC shows the complex scale factor, and compensation of such scale factor necessitates the complex hardware. The complexity of R4HR CORDIC is reduced by pre-computing the scale factor for initial iterations and by employing scaling-free rotations for later iterations. Quantitative hardware analysis suggests better hardware utilization than the recent approaches. The proposed architecture is implemented on a Virtex-6 FPGA, and FPGA implementation demonstrates $$19\%$$ 19 % less hardware utilization with better error performance than the approach with the radix-2 CORDIC algorithm.

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Section: Introductionmentioning

confidence: 99%

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Changela,

Kumar,

Woźniak

et al. 2023

Sci Rep

View full text Add to dashboard Cite

show abstract

“…The CORDIC algorithm was first proposed in 1959 by E. Volder for computing trigonometric functions, multiplication and division [11,12]. To expand the usage areas, the CORDIC algorithm is applied in the computation of logarithms, exponentials, square roots, arbitrary Nth root, complex operations [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. In the implementation of the CORDIC algorithm, the type of computation (addition or subtraction) in the iteration is determined by the rotation direction.…”

Section: Introductionmentioning

confidence: 99%

An optimized hardware implementation of the CORDIC algorithm

Lyu

Wang

et al. 2022

IEICE Electron. Express

Self Cite

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In this paper, we propose a software-based simulator and an optimized hardware implementation of the CORDIC algorithm. The number of iterations and the bit width are selected by their relationship calculated by the simulator to satisfy precision requirement. In the proposed hardware implementation, the addition and subtraction operations share the hardware resources. The two's complement is calculated in two steps: inverting and adding one. The adding one operation is integrated in the addition component of the iteration. In addition, a 3:2 compressor is used to reduce the number of adders, and a carry look-ahead adder is used to reduce the critical path. The synthesized results show that when compared with state-of-the-art designs, our method reduces the area by 53.79% and the delay by 58.97% while maintaining the same precision.

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“…In the fields of electronic circuits, communication systems and signal processing, complex numbers are widely used for real-time data representation and system modeling [1]- [3]. However, the current researches mostly focus on the Nth root of real numbers [4]- [6] and rarely about that of complex numbers. Typically the complex Nth root operations are implemented by software which adopts various algorithms to guarantee accurate and reliable computations.…”

Section: Introductionmentioning

confidence: 99%

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation

Chen

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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As the existing complex number Nth root computation methods are relatively discrete, we propose a general method and architecture based on coordinate rotation digital computer (CORDIC) to compute arbitrary complex number Nth root for the first time. Our method performs the tasks of computing complex modulus, complex phase angle, real Nth root, sine function and cosine function, which can be implemented by circular CORDIC, linear CORDIC and hyperbolic CORDIC. Based on these CORDICs, our proposed architecture can not only improve the hardware efficiency just through shift-add operations, but also flexibly adjust the precision and the input range of complex number Nth root. To prove its feasibility, we conduct a software simulation and implement an example circuit in hardware. Under the TSMC 28nm CMOS technology, we synthesize it and get the report that it has the area of 6561µm 2 and the power of 3.95mW at the frequency of 1.5GHz.

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CORDIC-Based Architecture for Computing Nth Root and Its Implementation

Cited by 30 publications

References 28 publications

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

An optimized hardware implementation of the CORDIC algorithm

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation

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