Copper gate hydrogenated amorphous silicon TFT with thin buffer layers

Lee, Sang Wook; Cho, Kyu Sik; Choo, Byung Kwon; Jang, Jin

doi:10.1109/led.2002.1004223

Cited by 10 publications

(3 citation statements)

References 12 publications

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“…However, the Cu adhesion is insufficient and there is a risk of peeling off; secondly, Cu may diffuse into the active layer and form a deep energy level, resulting in a deterioration of TFT performance. To avoid the above problems, a buffer layer should be deposited before growing Cu, which can enhance the adhesion of Cu and acts as a diffusion barrier [4][5][6][7][8] . The patterning of Cu electrodes is achieved by photolithography and wet etching, and the CD Bias and profile angle(PA) after etching are two important parameters to characterize the etching performance [9][10][11] .…”

Section: Introductionmentioning

confidence: 99%

P‐7.11: Effect of etching conditions, MoNb thickness on gate profile and CD Bias of ADS Pro TFT

Liu,

Chen,

Huang

et al. 2024

Symp Digest of Tech Papers

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The etched MoNb/Cu stack film is widely used as gate electrodes for ADS Pro TFTs. The CD Bias and profile angle(PA) are two important performance parameters for wet etching. The product‐specific bottom MoNb thickness and the fluctuation of wet etching conditions(time, temperature, and Cu ion concentration) make it difficult to precisely control the etching quality, thus it is of great significance to identify the influence of the above two factors on CD Bias and PAs. In this paper, the wet etching time, temperature and Cu ion concentration are taken as independent variables, and 11 different etching conditions are arranged based on the uniform experiments design to etch MoNb/Cu samples with two different MoNb thicknesses. The experiments reseluts shows that for the etched two MoNb/Cu stacks (15/300 nm, 30/300 nm) samples, the CD Bias and PAs are in the range of 0.22~0.73 µm and 40~51°, respectively. Both the CD Bias and PAs increase with the bottom MoNb thickness, etching temperature, etching time or Cu concentration, and the PAs increases with CD Bias. The etchant may form a reflux path during the etching process, along which the etching rate decreases. The difference between the etching rates at the top and bottom of the electrode contributes to the increase of PAs and CD Bias with etching severity. In the MoNb/Cu sidewall, MoNb acts as an anode due to the low corrosion potential, and the galvanic effect leads to the acceleration of MoNb etching, which ultimately results in the increase of PA and CD Bias under the thick MoNb.

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Section: Introductionmentioning

confidence: 99%

P‐7.11: Effect of etching conditions, MoNb thickness on gate profile and CD Bias of ADS Pro TFT

Liu,

Chen,

Huang

et al. 2024

Symp Digest of Tech Papers

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“…To reduce the signal delay in TFT-LCDs (Thin Film Transistor Liquid Crystal Display), Cu metallization with superior electromigration resistance, inhibiting hillock information, and low resistivity compared to Al has received considerable attention as a potential interconnection material 1 . However, the use of Cu leads to poor adhesion to the glass substrate, the oxidation of exposed Cu surface and high reactivity with precursors of SiN during PECVD (Plasma-Enhanced Chemical Vapor Deposition) process 1,2 . For this purpose, capping layers such as Cr 2 O 3 3 and CuMg 4 alloy have been widely tested.…”

Section: Introductionmentioning

confidence: 99%

Selective Electroless Ni-Based Capping Layer on Cu Gate Electrode of TFT-LCD

et al. 2007

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In this study, electroless Ni-based capping layers were selectively deposited on Cu surface without Pd activation. The Pd-free electroless process can eliminate possible Pd diffusion into Cu lines that causes an increase in sheet resistance of Cu. Film composition, surface morphology, film structure, chemical state and barrier function of electroless Ni-based films were discussed in our present work. The developed NiWMoB films have superior thermal stability compared with NiWB film. In addition, the depth profile suggested Cu diffusion was not observed after thermal treatment, rendering it a promising candidate as capping layer.

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“…1,2) Recently, owing to its success in fabricating ultralarge-scale integration (ULSI) circuits, Cu metallization has attracted much attention as a future technology for active matrix liquid crystal displays (AM-LCDs). [3][4][5][6][7] From past experience in the Cu metallization of ULSI circuits, a multilayer consisting of a barrier layer and a conductive seed layer is necessary to produce a Cu gate electrode for TFTs by electrodeposition. The deposition of a barrier layer prior to Cu metallization can prevent Cu from diffusing into the glass substrate in TFTs, and the barrier layer can also act as an adhesion layer.…”

mentioning

confidence: 99%

Forming Tapered Pattern by Cu Electrodeposition Through Mask on Ni Seed Layer for Thin-Film Transistors

Jenq

Wan

Wang

et al. 2006

jjap

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The fabrication of Cu gates for thin-film transistors (TFTs) by electrodeposition through mask on a Ni layer has been developed. After pretreatment in acid sulfate solution, a Cu deposit acquires the property of good adhesion on a Ni layer. Organic additives [e.g., poly(ethylene glycol) (PEG), bis(3-sodiumsulfopropyl) disulfide (SPS)] were used to create the desired tapered shape of the deposited Cu pattern on a Ni layer. Furthermore, a multilayer Cu gate for TFTs was fabricated after the selective etching of the nickel layer. The new method provides an alternative wet process for fabricating Cu gates for TFTs.

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Copper gate hydrogenated amorphous silicon TFT with thin buffer layers

Cited by 10 publications

References 12 publications

P‐7.11: Effect of etching conditions, MoNb thickness on gate profile and CD Bias of ADS Pro TFT

P‐7.11: Effect of etching conditions, MoNb thickness on gate profile and CD Bias of ADS Pro TFT

Selective Electroless Ni-Based Capping Layer on Cu Gate Electrode of TFT-LCD

Forming Tapered Pattern by Cu Electrodeposition Through Mask on Ni Seed Layer for Thin-Film Transistors

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