Coping with Data Dependencies of Multi-dimensional Array References

Abstract

This paper presents a new static data dependence analysis approach, Dependence Difference Inequality Test, which can deal with coupled subscripts for multi-dimensional array references for software pipelining techniques for nested loops. The Dependence Difference Inequality Test (DDIT) replaces direction vectors with dependence difference inequalities as constraints to variables in a linear system. The method presented in this paper extends the applicable range of the Generalized Lambda Test and seems to be a practical scheme to analyze data dependence. Experimental results show that the number of data independences checked by the DDIT algorithm is slightly smaller than that manually. It is also shown that our method is better than other traditional data dependence analysis methods without increasing time cost: it increases the success rate of the Generalized Lambda Test by approximately 14.19%.

A Static Data Dependence Analysis Approach for Software Pipelining

“…Further experimental results are reported in [12]. On the other hand, a dynamic data dependence analysis approach is presented in [13], which can work with this method together to coping with data dependencies for software pipelining.…”

A Dynamic Data Dependence Analysis Approach for Software Pipelining

“…op6 (3) op7 (2) op1 (5) op5 (4) op8 (1) RTPAD(op5 (5) , op8 (2) ) RTPAD(op5 (5) , op8 (3) ) RTPAD(op5 (5) , op8 (4) ) 6…”

“…op6 (6) op7 (5) op1 (8) op9 (3) op5 (7) op8 (4) RTPAD(op5 (8) , op8 (5) ) RTPAD(op5 (8) , op8 (6) ) RTPAD(op5 (8) , op8 (7) ) 9 op6 (7) op7 (6) op1 (9) op9 (4) op5 (8) op8 (5) RTPAD(op5 (9) , op8 (6) ) RTPAD(op5 (9) , op8 (7) ) RTPAD(op5 (9) , op8 (8) ) Table 2. An address conflict between op 5 (6) and op 8 (4) is detected…”

“…op7 (5) NOP NOP op9 (3) NOP NOP Op8 (4) RTPAD(op5 (8) , op8 (5) ) RTPAD(op5 (8) , op8 (6) ) RTPAD(op5 (8) , op8 (7) ) 9 NOP NOP op1 (7) op5 (6) 10 op6 (6) NOP NOP op1 (8) NOP NOP op5 (7) NOP NOP NOP NOP NOP NOP NOP NOP 11 op6 (7) op7 (6) op1 (9) op9 (4) op5 (8) op8 (5) RTPAD(op5 (9) , op8 (6) ) RTPAD(op5 (9) , op8 (7) ) RTPAD(op5 (9) , op8 (8) The prologue stage of the loop is from cycle 1 to cycle 5, and the pipelining stage of the loop begins from cycle 6. In Table 1, each VLIW instruction executes 6 operations belonging to adjoining iterations, namely, it takes a VLIW CPU one cycle to complete an iteration of the loop.…”

“…To exploit instruction-level parallelism (ILP), compilers for a very-long instruction word (VLIW) machine often employ static code scheduling and software pipelining [1] [2] [3] [4]. It is, however, restricted by ambiguous dependencies between memory fetches.…”