Coordinated parallelizing compiler optimizations and high-level synthesis

Abstract

We present a framework for high-level

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

“…The front-ends exchange information with the back-ends using intermediate formats, such as the Electronic Design Interchange Format (EDIF) [9,10], used by most E-CAD tools. Complex control flow optimization has been evaluated in [2,11,12], but for small parts of code and by no means complete application tests [13], discusses synthesis for distributed logic and memory [14] uses communicating processes as a system specification medium. HLS methods that include memory access management are outlined in [1], where digital signal processing (DSP) and streaming applications are synthesized using performance constraints [15], analyses mutually exclusive scheduling on extended data-flow graphs (EDFG) [16] synthesizes behavioural descriptions with time constraints, where complex operations are decomposed into simpler ones, and a similar set of decomposed fragments of operators, with the same pattern, are scheduled in a clock cycle.…”

“…In [18] the SURYA system utilises the Simplify theorem prover to prove that the RTL model generated by HLS tools is functionally-equivalent to the specification. SURYA found two bugs in the SPARK HLS tool [2], which were until then unknown. In [19] flip-flops are replaced with latches so as to improve implementation timing, since latches are inherently more tolerant to process variations than flip-flops.…”

“…During the last couple of decades, commercial and academic organisations have invested in HLS and optimisation techniques, so as to achieve design automation, quality of implementations and short specification-to-product times [1,2]. However, existing HLS tools are not widely accepted by the engineering community because of their poor results, especially for large applications with complex module and control-flow hierarchy.…”

Μεθοδολογίες Αυτοματοποιημένης Εξερεύνησης Και Σύνθεσης Επαναδιατάξιμων Συνεπεξεργαστών Υλικού

“…Conventional operation chaining targeted data-flow behavioral descriptions [6], [7] for performance improvement. Recently, operation chaining across conditional boundaries has been enabled [97] for designs with mixed data-flow and control-flow structures. Many researchers have also proposed to perform DSE by investigating the duality between timing-and resource-constrained scheduling problems [4], [8], [5].…”

“…We consider a minimum delay resource constrained operation scheduling algorithm found in [97]. Each examined resource allocation (#Alus, #Muls, #MemPorts) forms the actual resource constraints that the scheduler has to satisfy.…”