COOL interconnect low power interconnection technology for scalable 3D LSI design

Chacin, Marco; Uchida, Hirohisa; Hagimoto, Michiya; Miyazaki, Takashi; Ohkawa, Takenao; Ikeno, Rimon; Matsumoto, Yukoh; Imura, Fumito; Suzuki, Motohiro; Kikuchi, Katsuya; Nakagawa, Hiroshi; Aoyagi, Masahiro

doi:10.1109/coolchips.2011.5890921

Cited by 9 publications

(1 citation statement)

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“…TSVs and bumps are placed as an array in the central area of a stackable IC. "Cool Interconnect" is a new three-dimensional heterogeneous multi-IC scalable stacking architecture which we have proposed to reduce wire length, reduce the size of bus driver circuits and reduce the number of repeater circuits [5]- [7]. Fig.…”

Section: Cool Interconnect Test Chipmentioning

confidence: 99%

Method for back-annotating per-transistor power values onto 3DIC layouts to enable detailed thermal analysis

Melamed

Imura

Aoyagi

et al. 2014

2014 International Conference on Electronics Packaging (ICEP)

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In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large spikes in individual device temperatures. These "hotspots" must be carefully analyzed at design time to ensure that the device temperatures will not cause the circuit to malfunction, and to assess the device temperature's impact on the longevity of the circuit. In this paper we present a tool flow for capturing accurate per-transistor power values in standard cell designs to allow for detailed thermal analysis. After extracting power values, High Definition Power Blurring is used to analyze the thermal performance of the inter-chip communication bus of a "Cool Interconnect" chip.

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Section: Cool Interconnect Test Chipmentioning

confidence: 99%