Convolutional Neural Network (CNN) Accelerator Chip Design

Ma, Xinran; Ruiyong, Zhao; Zhou, Jianyang

doi:10.1109/icasid.2019.8925182

Cited by 1 publication

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“…To accelerate the CNN accelerator design, several works focus on either providing an early‐stage simulator to help researchers explore the design space [48, 49], or implementation guidelines [50]. These works so far still do not support the sparse CNN models.…”

Section: Related Workmentioning

confidence: 99%

Dataflow and microarchitecture co‐optimisation for sparse CNN on distributed processing element accelerator

Pham

Lai

2020

IET Circuits, Devices & Systems

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Accelerators that utilise the sparsity of both activation data and network structure of convolutional neural networks (CNNs) have demonstrated efficient processing of CNNs with superior performance. Previous research studies have shown three critical design concerns when designing accelerators for sparse CNNs, including data reuse, parallel computing performance, and effective sparse computation. These factors were each used in the previous accelerator designs, but none of the designs have considered all the factors at the same time. This study provides analytical approaches and experimental results to reveal the insight of accelerator design for sparse CNNs. The authors have shown that the architectural aspects need to be all considered to avoid performance pitfalls, including their mutual effects. Based on the proposed analytical approach, they proposed enhancement techniques and co-designed among the factors discussed in this study. The improved architecture shows up to 1.5× data reuse and/or 1.55× performance improvement in comparison with state-of-the-art sparse CNN accelerators while still maintaining equal area and energy cost.

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Section: Related Workmentioning

confidence: 99%