Convolutional Neural Network Based Heart Sounds Recognition on Edge Computing Platform

Low-Cost FPGA Implementation of Deep Learning-Based Heart Sound Segmentation for Real-Time CVDs Screening

“…Nonetheless, it shows the state-of-the-art in this field, setting the basis for further research to improve accuracy, reduce inference times or lower the power consumption. Firstly, the clock frequency of this implementation is 4.8 times lower than the one employed in [20] and 15 times lower than in [21]. This, together with the fact that FPGAs are less power demanding than CPUs would expectedly imply a significant decrease in the power consumption of this implementation compared to the other two.…”

“…Given this, it is clear that our model has significantly more complex than the other two. For this reason, the classification results reported in this work achieved a more accurate segmentation considering the four heart sound components of a PCG, whereas [20] distinguished between S1, S2 and the rest of the signal, and [21] limited the model to only systole and diastole detection. Note that the three models have been trained with different datasets, so performance may depend on this factor.…”

“…Kwiatkowski et al [20] implemented a small CNN in an ARM Cortex M7 processor with an inference time of 11 ms, using an 8-bit representation. Vakamullu et al [21] used a Raspberry Pi 3B (quad-core ARM Cortex A53) to implement a 1-dimensional CNN. They used different combinations of the decimation factor of the data and kernel size of the CNN to fit the model on the targeted device.…”

“…All works have used a CNN to perform the segmentation, differing in their architecture. Kwiatkowski et al [20] used three convolutional layers with intercalated maxpooling and batch-normalization layers, and Vakamullu et al [21] implemented just two convolutional layers followed by max-pooling layers. Our model has 23 convolutional layers, and uses the U-Net architecture, with encoding and decoding stages.…”

“…Thus, equivalent or even lower inference times could be achieved by porting this design to an FPGA with a higher clock frequency. The work presented in [21] did not report any inference times for their implementation.…”