2020
DOI: 10.15276/eltecs.33.109.2020.3
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Conveyor Model and Implementation of the Real Numbers Adder on Fpga

Abstract: The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, … Show more

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