Conveyor-mode single-electron shuttling in Si/SiGe for a scalable quantum computing architecture

Inga, Seidler,; Struck, Tom; Xue, Ruyi; Focke, Niels K.; Trellenkamp, Stefan; Bluhm, Hendrik; Schreiber, Lars R.

doi:10.48550/arxiv.2108.00879

Cited by 6 publications

(10 citation statements)

References 35 publications

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“…Coherent spin shuttling has been realized over effective several-micrometer distances in a GaAs quantum dot circuit [56]. Reliable charge shuttling has also been shown in multi-dot Si/SiGe arrays [57,58], while repeated coherent spin tunneling between two Si-MOS dots has also been demonstrated [59]. This places shuttling as a top candidate for micron-scale on-chip quantum information transport in near-term devices.…”

Section: Shuttlingmentioning

confidence: 95%

Multicore Quantum Computing

Jnane,

Undseth,

Cai

et al. 2022

Preprint

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Any architecture for practical quantum computing must be scalable. An attractive approach is to create multiple cores, computing regions of fixed size that are well-spaced but interlinked with communication channels. This exploded architecture can relax the demands associated with a single monolithic device: the complexity of control, cooling and power infrastructure as well as the difficulties of cross-talk suppression and near-perfect component yield. Here we explore interlinked multicore architectures through analytic and numerical modelling. While elements of our analysis are relevant to diverse platforms, our focus is on semiconductor electron spin systems in which numerous cores may exist on a single chip. We model shuttling and microwave-based interlinks and estimate the achievable fidelities, finding values that are encouraging but markedly inferior to intra-core operations. We therefore introduce optimsed entanglement purification to enable highfidelity communication, finding that 99.5% is a very realistic goal. We then assess the prospects for quantum advantage using such devices in the NISQ-era and beyond: we simulate recently proposed exponentially-powerful error mitigation schemes in the multicore environment and conclude that these techniques impressively suppress imperfections in both the inter-and intra-core operations.

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Section: Shuttlingmentioning

confidence: 95%

Multicore Quantum Computing

Jnane,

Undseth,

Cai

et al. 2022

Preprint

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“…Our main idea is to connect a few control lines to a small number of gate sets (i.e. clavier gates set to the same potential), the number of which is independent of the length of the coherent link [47]. The constant number of input terminals of the coherent link solves the signal fan-out problem and assures full scalability of our approach.…”

Section: A Requirements Posed By Scalabilitymentioning

confidence: 99%

“…We discuss two distinct transport modes: The first -the "bucketbrigade" (BB) mode -relies on periodic modulation of voltages controlling relative detunings between adjacent QDs in a pre-existing chain of N ≈ 100 tunnel-coupled QDs [32]. The second -the "conveyor belt" (CB) moderelies on electrostatic creation of a single deep quantum dot that is moving along a one-dimensional channel [47]. After introducing these two modes, we give arguments for BB mode being less robust than the CB mode when scalability of the quantum computing architecture is seriously taken into account in presence of realistic electrostatic disorder.…”

Section: Introductionmentioning

confidence: 99%

Blueprint of a scalable spin qubit shuttle device for coherent mid-range qubit transfer in disordered Si/SiGe/SiO$_2$

Langrock¹,

Krzywda²,

Focke³

et al. 2022

Preprint

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Silicon spin qubits stand out due to their very long coherence times, compatibility with industrial fabrication, and prospect to integrate classical control electronics. To achieve a truly scalable architecture, a coherent mid-range link between qubit registers has been suggested to solve the signal fan-out problem. Here we present a blueprint of such a ∼ 10 µm long link, called a spin qubit shuttle, which is based on connecting an array of gates into a small number of sets. The number of these gate sets and thus the number of required control signal is independent of the link distance to coherently shuttle the electron qubit. We discuss two different operation modes for the spin qubit shuttle: A qubit conveyor, i.e. a potential minimum that smoothly moves laterally, and a bucket brigade, in which the electron is transported through a series of tunnel-coupled quantum dots by adiabatic passage. We find the former approach more promising considering a realistic Si/SiGe device including potential disorder from the charged defects at the Si/SiO2 layer, as well as typical charge noise. Focusing on the qubit transfer fidelity of the conveyor shuttling mode, motional narrowing, the interplay between orbital and valley excitation and relaxation in presence of g-factors that depend on orbital and valley state of the electron, and effects from spin-hotspots are discussed in detail. We find that a transfer fidelity of 99.9 % is feasible in Si/SiGe at a speed of ∼10 m/s, if the average valley splitting and its inhomogeneity stay within realistic bounds. Operation at low global magnetic field ≈ 20 mT and material engineering towards high valley splitting is favourable to reach high transfer fidelities.

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“…Four phase-shifted sinusoidal signals are applied to four consecutive gates (shades of blue in Fig. 2), repeating the set of signals along the linear array to create a travelingwave potential to trap and shuttle an electron [13,25]. The sign of the phase difference between adjacent gates defines the shuttling direction.…”

Section: Array Design and Operationmentioning

confidence: 99%

“…In addition, the ∼ 100 nm spatial dimensions intrinsic to semiconductor spin qubits provide the potential to pack many millions of qubits inside a single quantum processor chip. The last several years have seen significant progress in spin-qubit research that resulted in the demonstration of long coherence times [3], high-fidelity single- [3][4][5] and two-qubit gates [6,7], quantum algorithms [8], quantum non-demolition measurements [9,10], and electron spin [11] and charge [12,13] transfer.…”

Section: Introductionmentioning

confidence: 99%

The spider-web array--a sparse spin qubit array

Boter,

Dehollain,

van Dijk

et al. 2021

Preprint

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One of the main bottlenecks in the pursuit of a large-scale-chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional (2D) array with ∼12 µm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling leading to a Rent's exponent as low as p = 0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit processor. This work presents a novel and complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and significantly closing the gap towards a fully CMOS-compatible quantum computer implementation.

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Conveyor-mode single-electron shuttling in Si/SiGe for a scalable quantum computing architecture

Cited by 6 publications

References 35 publications

Multicore Quantum Computing

Multicore Quantum Computing

Blueprint of a scalable spin qubit shuttle device for coherent mid-range qubit transfer in disordered Si/SiGe/SiO$_2$

The spider-web array--a sparse spin qubit array

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