Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

Abstract

To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruction-level parallelism (ILP) and thread-level parallelism (TLP). Wide-issue superscalar processors exploit ILP by executing multiple instructions from a single program in a single cycle. Multiprocessors (MP) exploit TLP by executing different threads in parallel on different processors. Unfortunately, both parallel processing styles statically partition processor resources, thus preventing them from adapting to dynamically changing levels of ILP and TLP in a program. With insufficient TLP, processors in an MP will be idle; with insufficient ILP, multiple-issue hardware on a superscalar is wasted. This article explores parallel processing on an alternative architecture, simultaneous multithreading (SMT), which allows multiple threads to compete for and share all of the processor's resources every cycle. The most compelling reason for running parallel applications on an SMT processor is its ability to use thread-level parallelism and instruction-level parallelism interchangeably. By permitting multiple threads to share the processor's functional units simultaneously, the processor can use both ILP and TLP to accommodate variations in parallelism. When a program has only a single thread, all of the SMT processor's resources can be dedicated to that thread; when more TLP exists, this parallelism can compensate for a lack of per-thread ILP. We examine two alternative on-chip parallel architectures for the next generation of processors. We compare SMT and small-scale, on-chip multiprocessors in their ability to exploit both ILP and TLP. First, we identify the hardware bottlenecks that prevent multiprocessors from effectively exploiting ILP. Then, we show that because of its dynamic resource sharing, SMT avoids these inefficiencies and benefits from being able to run more threads on a single processor. The use of TLP is especially advantageous when per-thread ILP is limited. The ease of adding additional thread contexts on an SMT (relative to adding additional processors on an MP) allows simultaneous multithreading to expose more parallelism, further increasing functional unit utilization and attaining a 52% average speedup (versus a four-processor, single-chip multiprocessor with comparable execution resources). This study also addresses an often-cited concern regarding the use of thread-level parallelism or multithreading: interference in the memory system and branch prediction hardware. We find that multiple threads cause interthread interference in the caches and place greater demands on the memory system, thus increasing average memory latencies. By exploiting thread-level parallelism, however, SMT hides these additional latencies, so that they only have a small impact on total program performance. We also find that for parallel applications, the additional threads have minimal effects on branch prediction.

L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy

“…SMT is aimed at masking not only DRAM latency, but also other causes of pipeline stalls, by having hardware support for more than one active thread [22]. SMT can therefore be considered a solution to a wider range of CPU performance problems than RAMpage.…”

“…SMT, while adding hardware complexity, is an established approach [22], and there are existing implementations [5].…”

A new memory monitoring scheme for memory-aware scheduling and partitioning

“…The scheme becomes increasingly important as more and more processes and threads share various memory resources in computers using SMP [2,7,8], Multiprocessor-on-a-chip [3], or SMT [21,10,4] architectures.…”

Power-sensitive multithreaded architecture

“…Simultaneous multithreading has been shown to be an effective architecture to increase processor throughput both in multiprogrammed [15,14] and parallel execution [10]. Previous work has demonstrated SMT's reduced dependence on speculation to achieve parallelism [14,8].…”