Controlling work in process during semiconductor assembly and test operations

Zhang, Chuwen; Bard, Jonathan F.; Chacon, Rodolfo

doi:10.1080/00207543.2017.1333649

Cited by 6 publications

(4 citation statements)

References 27 publications

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“…The work-in-process (WIP) information of each machine is of primary importance to monitor the performance of the whole wafer fab and a balanced WIP distribution over a successive period of time contributes to meeting the product demand. 36 The forth dataset is a benchmark dataset which is formed by 2405 time-varying hierarchical datasets. 37 This dataset includes low, regular and spiky node value changes and hierarchy structure changes.…”

Section: Evaluation Of Perceptual Propertiesmentioning

confidence: 99%

Voronoi treemap in Manhattan distance and Chebyshev distance

Wang

Xing

Zhang

2023

Information Visualization

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The ordinary Voronoi treemap generated based on the Euclidean distance function has the flexibility to slightly adjust the layout when visualizing time-varying hierarchical data for better visual quality, preserving neighborhood relationships, and preserving a stable layout. However, its layout formed by segments with arbitrary orientations has poor shape stability between successive layouts at different time indexes, which is not conducive for the users to understand the plot and track the same node. In this paper, we propose novel Voronoi treemaps in Manhattan distance and Chebyshev distance respectively, such that the segments in the new layouts only have four orientations (horizontal, vertical, and ±45° to the [Formula: see text]-axis). The new layouts can not only heritage the abilities of ordinary Voronoi treemap, but preserve good shape stability. To achieve this, we first focus on the weighted bisector between two sites in Manhattan distance and design a bisector generation method for different weight values of two sites, as the bisector is the foundation to form a diagram. Then a divide-and-conquer method is utilized to form the bisectors into a Voronoi diagram, and a Voronoi treemap layout can be finally obtained by using Lloyd’s method to iteratively adjust the diagram. Moreover, we prove that the treemap algorithm in Manhattan distance can be adjusted to also generate the Voronoi treemap in Chebyshev distance via linear transformation, avoiding designing additional algorithm. The computational properties of the proposed methods are first evaluated to check whether the layouts can be generated fast and accurately. Then the perceptual properties are evaluated quantitatively and qualitatively based on quality metrics and user studies, respectively. The results demonstrate that the proposed Voronoi treemaps preserve similar layout stability, but better visual quality and shape stability than the ordinary Voronoi treemap. Our algorithms are simple and resolution-independent, but also provide alternatives to the Voronoi treemaps.

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Section: Evaluation Of Perceptual Propertiesmentioning

confidence: 99%

Voronoi treemap in Manhattan distance and Chebyshev distance

Wang

Xing

Zhang

2023

Information Visualization

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“…In the contemporary semiconductor packaging facilities, maximizing machine utilization and minimizing the flow time jobs are very important objectives [3], [4]. The former improves the production efficiency and the latter enables manufacturers to flexibly respond to the fluctuations in demand of semiconductor markets [5]. Unfortunately, it is challenging to optimize these two performance measures at the same time [6], [7].…”

Section: Introductionmentioning

confidence: 99%

A Generation and Repair Approach to Scheduling Semiconductor Packaging Facilities Using Case-Based Reasoning

Park

Huh²,

Park

2023

IEEE Access

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As the demand for multi-chip products with high capacity and small size increases, semiconductor packaging facilities have been faced with complicated constraints such as re-entrant flows, sequence dependent setups, and alternative routes, which leads to difficulties in scheduling semiconductor manufacturing operations. Furthermore, due to the frequent variations in the relative importance between objectives as well as the variabilities in initial setup status, available machines, and production requirements, practitioners are obliged to obtain a schedule within a short amount of computation time. In this paper, we propose a novel two-phase framework that aims to quickly produce a schedule of semiconductor packaging facilities by using case-based reasoning for minimizing the weighted sum of machine loss time and waiting time of jobs. Specifically, in the case generation phase, a case database is constructed by solving case scheduling problems using an existing solver. The case reasoning phase is responsible for repairing operation type sequences in the cases to produce a schedule for an unseen scheduling problem whose production requirements, available machines, initial setup status, and weight between performance measures are different from those of cases. The extensive experimental results demonstrated that the proposed approach requires a short computation time similar to the rule-based methods while maintaining the quality of the schedules comparable to that of the existing metaheuristics.INDEX TERMS Semiconductor packaging facilities, flexible job shop scheduling, case-based reasoning, sequence dependent setups, schedule repair.

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“…(1) The semiconductor wafer fabrication system is extremely complex and huge (as shown in Figure 1a), and its complex production process of multiple re-entrant flow [7] leads to multiple factors of influencing CT, as well as a complex interaction relationship [8].…”

Section: Introductionmentioning

confidence: 99%

“…Mathematics 2021, 9, x FOR PEER REVIEW 2 of 11 (1) The semiconductor wafer fabrication system is extremely complex and huge (as shown in Figure 1a), and its complex production process of multiple re-entrant flow [7] leads to multiple factors of influencing CT, as well as a complex interaction relationship [8]. (2) The wafer CT fluctuates (as shown in Figure 1b) after the make-to-stock strategies are changed; however, at this time, there are little data available to predict the wafer CT.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Transfer Learning for Cycle Time Forecasting for Semiconductor Wafer Lot under Different Work in Process Levels

Wang

Gao

et al. 2021

Mathematics

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The accurate cycle time (CT) prediction of the wafer fabrication remains a tough task, as the system level of work in process (WIP) is fluctuant. Aiming to construct one unified CT forecasting model under dynamic WIP levels, this paper proposes a transfer learning method for finetuning the predicted neural network hierarchically. First, a two-dimensional (2D) convolutional neural network was constructed to predict the CT under a primary WIP level with the input of spatial-temporal characteristics by reorganizing the input parameters. Then, to predict the CT under another WIP level, a hierarchical optimization transfer learning strategy was designed to finetune the prediction model so as to improve the accuracy of the CT forecasting. The experimental results demonstrated that the hierarchically transfer learning approach outperforms the compared methods in the CT forecasting with the fluctuation of WIP levels.

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Controlling work in process during semiconductor assembly and test operations

Cited by 6 publications

References 27 publications

Voronoi treemap in Manhattan distance and Chebyshev distance

Voronoi treemap in Manhattan distance and Chebyshev distance

A Generation and Repair Approach to Scheduling Semiconductor Packaging Facilities Using Case-Based Reasoning

Hierarchical Transfer Learning for Cycle Time Forecasting for Semiconductor Wafer Lot under Different Work in Process Levels

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