Controller estimation for FPGA target architectures during high-level synthesis

Abstract

In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence, especially, if a certain data-path realization requires a huge number of states and/or control signals. This paper presents a new approach on controller estimation during high-level synthesis for FPGA-based target architectures. The estimator, presented in this paper can be invoked after or during every synthesis-step, i.e. allocation, scheduling and binding, respectively. By considering the controller influence on the overall area of a design, design space exploration can be made more accurate and less error prone. We present an approach for estimating area of the controller based on information which are easily accessible during each step of highlevel synthesis, so no explicit description of the controller, which usually will be generated after the binding, is necessary. This is particularly valuable in the allocation phase, where intensive design space explorations have to be done, based on fast and accurate estimates.

Accurate area estimation model for FPGA based Implementation

“…Regarding the target technology, current approaches target either ASIC-based designs [11][12] or FPGA-based designs [4][5][6][7][8][9][10][14][15][16][17][18][19][20].FPGA-based area estimators either incorporate a physical model for the FPGA and estimate the area by performing actual mapping [14],by using modelling equations of the FPGA functional resources [4][5][6][7][8][9][10][15][16][17], or by building a large database for all possible resources configurations [18][19].As the routing of signals between resources can consume extra area, this area is difficult to determine prior to placement and routing. Fortunately, this routing area does not usually constitute a very large fraction of the overall area for the small and medium designs [6].…”

An area estimation methodology for FPGA based designs at systemc-level

“…These activities can be roughly partitioned in two sets: those extracting information from RTL descriptions (VHDL, Verilog) and those extracting information form behavioral level descriptions. In the latter case, the problem is faced by translating behavioral descriptions (Matlab [5,6], other [7,8]) into VHDL-RT [5,6] or DFG [7]. Though these transformations are required whenever closefitting results are needed, the effort necessary to transform a high-level model into a more detailed model is not currently justified.…”

Low-level estimation at high-levels of abstraction in system-level design

“…[1] can predict performance for FPGA designs using floor plan, wire-delay, and clock path estimation, but requires synthesis to be performed and a RT-level description of the system available prior to estimation, which is costly during design space exploration. Presenting a partial solution, [3] predicts CLB usage for FPGA designs using a partially synthesized design, where the estimator attempts to predict the scheduling and binding of variables to speed estimation. However, this work is relatively limited to controller-type applications with binary-coded states.…”