Controlled formation and resistivity scaling of nickel silicide nanolines

Abstract

We demonstrate a top-down method for fabricating nickel mono-silicide (NiSi) nanolines (also referred to as nanowires) with smooth sidewalls and line widths down to 15 nm. Four-probe electrical measurements reveal that the room temperature electrical resistivity of the NiSi nanolines remains constant as the line widths are reduced to 23 nm. The resistivity at cryogenic temperatures is found to increase with decreasing line width. This finding can be attributed to electron scattering at the sidewalls and is used to deduce an electron mean free path of 6.3 nm for NiSi at room temperature. The results suggest that NiSi nanolines with smooth sidewalls are able to meet the requirements for implementation at the 22 nm technology node without degradation of device performance.

Heteroepitaxial Growth of Gold Nanostructures on Silicon by Galvanic Displacement

“…13,18,42 In the case of silicon, hydrofluoric acid is required to ensure continuous metallic growth since the spontaneously formed silicon oxide product is a dielectric, and would prevent further metal ion reduction. In the presence of HF (aq), the silicon oxide layer is dissolved in situ to form soluble SiF 6 2Ϫ (aq) species according to eq 1: 28 Figure 2 shows the formation of nanostructured gold films on single crystal shards of Si(111) and Si(100), and silicon nanowires, by immersion in dilute KAuCl 4 (aq) and HF (aq) for short periods of time (seconds to minutes). Plan view (top view) SEM images reveal more continuous growth of gold on Si(111) as opposed to Si(100), but cross-section SEM images show no appreciable difference in the thickness of the gold layer, ϳ10 nm in each case.…”

“…In Figure 5b for gold on Si(100), 11 additional spots are observed of which 9 can be indexed for intermetallics, and in Figure 5c, for a different region of gold on Si(100), 12 extra spots are observed of which 7 can be indexed for intermetallics. The spots in the Si(100) case correspond to the following intermetallics: Au 7 Si, Au 4 Si, Au 5 Si, Au 5 Si 2 ,Au 3 Si 2 ,Au 3 Si, and Au 2 Si. Similarly, six extra spots are observed in the diffraction pattern for a gold nanoparticle on a silicon nanowire (Figure 5d), three of which can be indexed to the Au 2 Si, Au 5 Si, and Au 7 Si intermetallics.…”

High-pressure phase transitions and equations of state in NiSi. I.Ab initiosimulations

“…Lavoie et al, 2006). Recent work (Li et al, 2009) has described the formation of NiSi nanolines with smooth sidewalls and widths as low as 15 nm, indicating that this material can satisfy the requirements of reduced size necessary for the so-called '22 nm technology mode' of CMOS devices introduced by the semiconductor manufacturers in 2011, and possibly also the further reductions to 16 and 11 nm modes scheduled for 2013 and 2015. The physical property of NiSi that shows the most striking behaviour is its thermal expansion.…”

Copper Metal for Semiconductor Interconnects

“…Surface scattering increases as the critical dimensions of the Cu line becomes smaller than the bulk mean free path of the electrons. To solve this issue, new material such as tungsten (W), silicides, carbon nanotube, or collective excitations could be an alternative to Cu as interconnects [42,43]. Even though the bulk resistivity of W and silicide films is much larger than that of Cu film, the shorter mean free path of the electrons will lower the surface scattering effect.…”