Controlled behaviour of STF in CT modulators

Maeyer, Jeroen De; Raman, Johan; Rombouts, Pieter; Weyten, L.

doi:10.1049/el:20051456

Cited by 37 publications

(19 citation statements)

References 4 publications

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“…{A(s)} * represents the star operator operating on A(s) [20]. It is a short notation for taking the Z-transform of the sampled inverse Laplace transform of A(s).…”

Section: Combined Outputmentioning

confidence: 99%

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

Vercaemer

Rombouts

2016

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents simple but accurate expressions for the noise components caused by clock jitter, in the output signal of Self-Oscillating Sigma Delta Modulators (SOSDMs). Contrary to conventional Continuous Time Sigma Delta Modulators (CTSDM), the SOSDM's loop contains a strong oscillation, whose attribution to the system's jitter caused noise has not previously been explored. In this paper, the SOSDM system is modeled, and the effect of the self oscillation, the input signal and the quantization noise on the jitter caused noise in the output signal, is calculated. Results are confirmed by system level simulations.

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“…{A(s)} * represents the star operator operating on A(s) [20]. It is a short notation for taking the Z-transform of the sampled inverse Laplace transform of A(s).…”

Section: Combined Outputmentioning

confidence: 99%

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

Vercaemer

Rombouts

2016

IEEE Trans. Circuits Syst. I

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“…The fourth step in the design methodology is to design a DT DSM with a unity-gain signal transfer function (STF(z) = 1). A designer can employ some feedforward paths from the input signal of the modulator and select their coefficients to achieve a flat STF [15]. As a simple solution, by using the topology of Fig.…”

Section: Excess Loop Delaymentioning

confidence: 99%

“…The STF(s) does not equal 1 exactly now due to the transformation approximation. As a better approximation, the bilinear approximation may be used, resulting in a more accurate conversion at the expense of much more complexity in the modulator since an extra feedforward path is needed in front of every integrator stage [15]. In our example, this is not used due to the design complexity.…”

Section: Excess Loop Delaymentioning

confidence: 99%

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

Radiom

Craninckx

et al. 2008

Analog Integr Circ Sig Process

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In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.

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“…Here, NTF denotes the noise transfer function while STF stands for the signal transfer function as defined in [6]. Concentrating on this first term, the input signal V in (s) is propagated through the STF after which it is sampled.…”

Section: Architecturementioning

confidence: 99%

Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators

Maeyer

Rombouts

Weyten

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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In this paper we present the design of a continuous time Σ∆-modulator in a 0.35 µm technology. While using a 6-bit internal quantizer a total of only 15 comparators were implemented. The inherent loop delay is accounted for in the design by using a design strategy based on the Nyquist stability criterion and the vector gain margin. Measurement results show a Peak SNR of 82 dB and a dynamic range of 85 dB for a bandwidth of 1.5 MHz.

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Controlled behaviour of STF in CT modulators

Cited by 37 publications

References 4 publications

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators

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