Control of limit cycle oscillations in a multiple‐sampled digitally controlled buck converter

Summary This paper presents a unified and exact nonaveraged approach to derive a frequency‐domain control‐oriented model for accurate prediction of the fast timescale dynamics and performances of switching converters with fixed frequency naturally sampled pulse width modulation and integrating feedback loop. Because the approach avoids averaging and approximations related to this process, a very good accuracy of the derived model is obtained. The main difference between the presented approach and the existing methodology for accurately predicting the behavior of switching converters is that, here, we break the feedback loop and we focus on analyzing the open‐loop gain and the effect of the system parameters on relative stability. This results in an approach much similar to control systems techniques rather than nonlinear dynamical system approaches. Consequently, the relative stability is tackled easily in the frequency domain. In particular, by treating the modulator as a gain depending on the operating point, the new model is formulated in such a way that standard control‐oriented tools such as Bode diagrams and root‐loci can be easily used. Therefore, the proposed approach gives some important issues like gain and phase margins that are highly useful in controller design. It is noticed that the crossover frequency, gain, and phase margins predicted by using the averaged model may deviate significantly from the actual values given by the proposed approach. The paper points out the sources of discrepancies and the theoretical results are validated by simulations using a circuit‐level switched model.

Section: Introductionmentioning

confidence: 88%

Nonaveraged control‐oriented modeling and relative stability analysis of DC‐DC switching converters

Al‐Turki

Aroudi

Mandal

et al. 2017

“…In this case, the SDM works at the limit-cycle mode. [10][11][12][13][14] This way, a linearized model may be attributed to the SDM for the sake of a simple mathematical analysis. This makes it possible to develop a new method for applying the NC technique in CTSDMs.…”

Section: Discussionmentioning

confidence: 99%

“…If a comparator is located inside an oscillatory closed‐loop system, its associated gain and phase can be calculated through the Barkhausen's criteria. In this case, the SDM works at the limit‐cycle mode . This way, a linearized model may be attributed to the SDM for the sake of a simple mathematical analysis.…”

Section: Introductionmentioning

confidence: 99%

An oscillatory noise‐shaped quantizer for time‐based continuous‐time sigma‐delta modulators

Tamaddon

Yavari

2017

Summary In this paper, a new type of an oscillatory noise‐shaped quantizer (NSQ) for time‐based continuous‐time sigma‐delta modulators is presented. The proposed NSQ is composed of an oscillatory voltage‐to‐time converter and a polyphase sampler. Using Tustin's transformation method and through the approximation of the comparator gain, a linearized model of the NSQ is introduced. This way, a novel realization of the first‐ and second‐order NSQ is presented. Its implementation is based on fully passive continuous‐time filters without needing any amplifier or power consuming element. The ploy‐phase sampler inside the NSQ is based on the combination of a time‐to‐digital and a digital‐to‐time converter. The layout of the proposed NSQ is provided in Taiwan Semiconductor Manufacturing Company 0.18 μm complementary metal‐oxide‐semiconductor 1P6M technology. The verification of the proposed NSQ is done via investigating both the system level and postlayout simulation results. Leveraging the proposed NSQ in an Lth‐order time‐based continuous‐time sigma‐delta modulator enhances the noise‐shaping order up to L + 2, confirming its superior effectiveness. This makes it possible to design high performance and wideband continuous‐time SDMs with low power consumption and relaxed design complexity.

“…A side advantage of APWM is that this architecture provides a low‐cost implementation by eliminating high‐quality carrier generator (sawtooth signal) . In addition to, due to the absence of the external sampling signal (e.g., the clock signal in the SDM), the APWM output signal is modulated as a continuous time signal without producing the quantization noise . Because of this property, the APWM modulators have attracted a lot of attention for having an excellent SNR performance controller and they can be applied to convert a single‐bit signal into a PWM signal which usually used in the control loop of the several power converting circuit.…”

Section: Introductionmentioning

confidence: 99%

“…3,9,11,12 In addition to, due to the absence of the external sampling signal (e.g., the clock signal in the SDM), the APWM output signal is modulated as a continuous time signal without producing the quantization noise. 3,[13][14][15] Because of this property, the APWM modulators have attracted a lot of attention for having an excellent SNR performance controller and they can be applied to convert a single-bit signal into a PWM signal which usually used in the control loop of the several power converting circuit. For example, they can be employed in inverter circuits, active filters, 14 class-D amplifiers, 16 Universal Mobile Transmitter Systems (UMTS), 17 ADSL/VDSL line drivers, 18,19 etc.…”

Section: Introductionmentioning

confidence: 99%

An asynchronous pulse width modulator for DC‐DC buck converter

Inanlou

Shoaei

Tamaddon

2019

Summary This paper presents an asynchronous pulse width modulation (APWM) approach for the analysis of a new class of the switched mode power supply (SMPS). The proposed APWM significantly simplified the mathematical analysis by utilizing a binary comparator (BAPWM) and a distinctive delay cell instead of hysteretic comparator. By this way, the mathematical analysis can be extended to study the behavior of high‐order self‐oscillating modulators in terms of key parameters such as the harmonic distortion and the stability. The performance of the proposed BAPWM is deeply analyzed for different orders of loop filters (here up to third order) in both time and frequency domain. To verify the effectiveness of the proposed analytical derivations, the BAPWMs are employed in a classic synchronous DC‐DC buck converter and its closed loop performance, in terms of stability, has been investigated. Then the converter is designed and simulated in 130‐nm CMOS technology to convert input voltage of 5 to 3.3 V with maximum load current of 1 A, using Spectre simulator. From the post‐layout simulation results, the peak efficiency conversion efficiency for 3.3 V output voltage is higher than 89%.