Control of Buffer-Induced Current Collapse in AlGaN/GaN HEMTs Using SiN<sub>x</sub> Deposition

Waller, William M.; Gajda, Mark; Pandey, Saurabh; Donkers, J.J.T.M.; Calton, David; Croon, J.A.; Šonský, Jan; Uren, Michael J.; Kuball, Martin

doi:10.1109/ted.2017.2738669

Cited by 28 publications

(19 citation statements)

References 26 publications

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“…Trapping effects at the surface states are responsible for the current collapse phenomenon of AlGaN/GaN HEMTs. In order to suppress the electron trapping effects, the passivation film must have positive charges to attract the trapped electrons [23][24][25][26][27]. The net charges of the SiN x film can be modified under the deposition conditions that alter the stoichiometry of SiN x .…”

Section: Resultsmentioning

confidence: 99%

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

et al. 2020

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We optimized a silicon nitride (SiNx) passivation process using a catalytic-chemical vapor deposition (Cat-CVD) system to suppress the current collapse phenomenon of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs). The optimized Cat-CVD SiNx film exhibited a high film density of 2.7 g/cm3 with a low wet etch rate (buffered oxide etchant (BOE) 10:1) of 2 nm/min and a breakdown field of 8.2 MV/cm. The AlGaN/GaN-on-Si HEMT fabricated by the optimized Cat-CVD SiNx passivation process, which had a gate length of 1.5 μm and a source-to-drain distance of 6 μm, exhibited the maximum drain current density of 670 mA/mm and the maximum transconductance of 162 mS/mm with negligible hysteresis. We found that the optimized SiNx film had positive charges, which were responsible for suppressing the current collapse phenomenon.

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Section: Resultsmentioning

confidence: 99%

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

et al. 2020

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“…The raw data for each test is a single-shot capture of a double-pulse event long after the dc-link has been energised to prevent the effect of current collapse [9] impacting the results. After a test sequence is complete, an automated MATLAB script on the host computer collects the captured data from the oscilloscope, together with ambient temperature and humidity data from the Xilinx system shown in Fig.…”

Section: Methods and Test Setupmentioning

confidence: 99%

“…4. Results for all data sets were also collected on the same day once equipment had reached stable operating temperatures, to minimise the impact of the memory effect that enhancement mode GaN FETs display [9], and to minimise the small day-to-day variation in the asynchronous timing circuits of the active gate driver.…”

Section: Methods and Test Setupmentioning

confidence: 99%

Stretching in Time of GaN Active Gate Driving Profiles to Adapt to Changing Load Current

Dalton

Dymond

Wang

et al. 2018

2018 IEEE Energy Conversion Congress and Exposition (ECCE)

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Active gate driving, where the gate signal is actively profiled, has been shown to reduce EMI, overshoot, and switching loss, in silicon power converters. Recently, much faster gate drivers with the ability to profile at a 100 ps resolution have been reported, which has opened up the possibility of actively driving emerging wide-bandgap devices. This could allow Gallium Nitride (GaN) and Silicon Carbide (SiC) FETs to be switched faster than is currently possible, as unwanted switching features such as current ringing at turn-on could be eliminated. However, these drivers have previously only been demonstrated with preprogrammed gate profiles that have been optimized at certain operating conditions, whereas converters typically operate in a range of conditions. In this paper, some limitations of using fixed gate profiles on GaN FETs are reported for the first time, and a new method of profile adaptation is demonstrated. First, the gate profiles in a 400 V GaN bridge-leg are optimized to minimize current ringing at turn-on for a given load current. Then, the load current is varied, showing that the gate signal profile remains close to optimal for ±20% changes in current. Also, over a larger range of at least ±35%, the profiled waveform performs better than a non-profiled gate waveform. It is then demonstrated that by slightly reducing the driver's internal clock frequency with increasing load current, the profile is re-optimized for new load currents. It is concluded that driver clock frequency adaptation may be a means of adapting gate profiles to load current variation and possibly also to temperature variation.

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“…In GaN power switching HEMTs, screening of the field has been achieved by allowing a positively charged layer to form under the drain [9]. Several solutions to supplying the necessary holes have been suggested including injectors near the drain [24], [25] or by controlling the leakage properties of the reverse biased diode under the 2DEG [26], [27]. The latter approach has allowed the current-collapse to be reduced to a few percent at temperatures up to 150°C [28], and clearly this approach is also successful in RF GaN-on-Si devices which do not show significant bulk-induced current collapse [1], [2], [29], [30].…”

Section: Suppression Of Back-gating Effectsmentioning

confidence: 99%

Buffer-Induced Current Collapse in GaN HEMTs on Highly Resistive Si Substrates

Chandrasekar

Uren

Eblabla

et al. 2018

IEEE Electron Device Lett.

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We demonstrate that the highly resistive Si substrate in GaN-on-Si RF HEMTs does not act as an insulator, but instead behaves as a conductive ground plane for static operation and can cause significant back-gateinduced current collapse. Substrate ramp characterization of the buffer shows good agreement with device simulations and indicates that the current collapse is caused by chargeredistribution within the GaN layer. Potential solutions, which alter charge storage and leakage in the epitaxy to counter this effect, are then presented.

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Control of Buffer-Induced Current Collapse in AlGaN/GaN HEMTs Using SiN_x Deposition

Cited by 28 publications

References 26 publications

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

Stretching in Time of GaN Active Gate Driving Profiles to Adapt to Changing Load Current

Buffer-Induced Current Collapse in GaN HEMTs on Highly Resistive Si Substrates

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Control of Buffer-Induced Current Collapse in AlGaN/GaN HEMTs Using SiNx Deposition

Cited by 28 publications

References 26 publications

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

Stretching in Time of GaN Active Gate Driving Profiles to Adapt to Changing Load Current

Buffer-Induced Current Collapse in GaN HEMTs on Highly Resistive Si Substrates

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Control of Buffer-Induced Current Collapse in AlGaN/GaN HEMTs Using SiN_x Deposition